set ::env(DESIGN_NAME) "wb_conbus_top"

set ::env(VERILOG_FILES) [glob ./designs/wb_conbus_top/src/*.v]

set ::env(CLOCK_PERIOD) "10.000"
set ::env(CLOCK_PORT) "clk_i"

set ::env(SYNTH_MAX_FANOUT)  5
set ::env(SYNTH_STRATEGY)    3
set ::env(PL_TARGET_DENSITY) 0.7
set ::env(FP_CORE_UTIL)      50
set ::env(FP_PDN_VPITCH)     153.6
set ::env(FP_PDN_HPITCH)     153.18
set ::env(FP_ASPECT_RATIO)   1
set ::env(GLB_RT_ADJUSTMENT) 0.15