Merge branch 'develop_newscl' of gitlab.com:efabless/foss/openlane into develop_newscl
diff --git a/designs/openstriVe_soc/src/striVe_soc.v b/designs/openstriVe_soc/src/striVe_soc.v
index 41dd8dc..6cdbe00 100644
--- a/designs/openstriVe_soc/src/striVe_soc.v
+++ b/designs/openstriVe_soc/src/striVe_soc.v
@@ -24,6 +24,7 @@
*/
`ifdef PICORV32_V
+`error "openstriVe_soc.v must be read before picorv32.v!"
`endif
/* Note: Synthesize register memory from flops */
@@ -232,7 +233,7 @@
assign resetn = ~(reset_delay[0] | ext_reset);
// ADC clock assignments
-
+
assign adc0_clk = (adc0_clksrc == 2'b00) ? rcosc_in :
(adc0_clksrc == 2'b01) ? spi_sck :
(adc0_clksrc == 2'b10) ? xtal_in :
@@ -250,9 +251,9 @@
assign gpio_out[2] = (rcosc_output_dest == 2'b01) ? rcosc_in : gpio[2];
assign gpio_out[3] = (rcosc_output_dest == 2'b10) ? rcosc_in : gpio[3];
assign gpio_out[4] = (rcosc_output_dest == 2'b11) ? rcosc_in : gpio[4];
- assign gpio_out[5] = (xtal_output_dest == 2'b01) ? xtal_in : gpio[5];
- assign gpio_out[6] = (xtal_output_dest == 2'b10) ? xtal_in : gpio[6];
- assign gpio_out[7] = (xtal_output_dest == 2'b11) ? xtal_in : gpio[7];
+ assign gpio_out[5] = (xtal_output_dest == 2'b01) ? xtal_in : gpio[5];
+ assign gpio_out[6] = (xtal_output_dest == 2'b10) ? xtal_in : gpio[6];
+ assign gpio_out[7] = (xtal_output_dest == 2'b11) ? xtal_in : gpio[7];
assign gpio_out[8] = (pll_output_dest == 2'b01) ? pll_clk : gpio[8];
assign gpio_out[9] = (pll_output_dest == 2'b10) ? pll_clk : gpio[9];
assign gpio_out[10] = (pll_output_dest == 2'b11) ? clk : gpio[10];
@@ -264,7 +265,7 @@
assign gpio_outenb[0] = (comp_output_dest == 2'b00) ? gpio_oeb[0] : 1'b0;
assign gpio_outenb[1] = (comp_output_dest == 2'b00) ? gpio_oeb[1] : 1'b0;
- assign gpio_outenb[2] = (rcosc_output_dest == 2'b00) ? gpio_oeb[2] : 1'b0;
+ assign gpio_outenb[2] = (rcosc_output_dest == 2'b00) ? gpio_oeb[2] : 1'b0;
assign gpio_outenb[3] = (rcosc_output_dest == 2'b00) ? gpio_oeb[3] : 1'b0;
assign gpio_outenb[4] = (rcosc_output_dest == 2'b00) ? gpio_oeb[4] : 1'b0;
assign gpio_outenb[5] = (xtal_output_dest == 2'b00) ? gpio_oeb[5] : 1'b0;
@@ -281,7 +282,7 @@
assign gpio_pullup[0] = (comp_output_dest == 2'b00) ? gpio_pu[0] : 1'b0;
assign gpio_pullup[1] = (comp_output_dest == 2'b00) ? gpio_pu[1] : 1'b0;
- assign gpio_pullup[2] = (rcosc_output_dest == 2'b00) ? gpio_pu[2] : 1'b0;
+ assign gpio_pullup[2] = (rcosc_output_dest == 2'b00) ? gpio_pu[2] : 1'b0;
assign gpio_pullup[3] = (rcosc_output_dest == 2'b00) ? gpio_pu[3] : 1'b0;
assign gpio_pullup[4] = (rcosc_output_dest == 2'b00) ? gpio_pu[4] : 1'b0;
assign gpio_pullup[5] = (xtal_output_dest == 2'b00) ? gpio_pu[5] : 1'b0;
@@ -298,7 +299,7 @@
assign gpio_pulldown[0] = (comp_output_dest == 2'b00) ? gpio_pd[0] : 1'b0;
assign gpio_pulldown[1] = (comp_output_dest == 2'b00) ? gpio_pd[1] : 1'b0;
- assign gpio_pulldown[2] = (rcosc_output_dest == 2'b00) ? gpio_pd[2] : 1'b0;
+ assign gpio_pulldown[2] = (rcosc_output_dest == 2'b00) ? gpio_pd[2] : 1'b0;
assign gpio_pulldown[3] = (rcosc_output_dest == 2'b00) ? gpio_pd[3] : 1'b0;
assign gpio_pulldown[4] = (rcosc_output_dest == 2'b00) ? gpio_pd[4] : 1'b0;
assign gpio_pulldown[5] = (xtal_output_dest == 2'b00) ? gpio_pd[5] : 1'b0;
@@ -435,8 +436,8 @@
.flash_io2_oeb (flash_io2_oeb),
.flash_io3_oeb (flash_io3_oeb),
- .flash_csb_ieb (flash_csb_oeb),
- .flash_clk_ieb (flash_clk_oeb),
+ .flash_csb_ieb (flash_csb_ieb),
+ .flash_clk_ieb (flash_clk_ieb),
.flash_io0_ieb (flash_io0_ieb),
.flash_io1_ieb (flash_io1_ieb),
@@ -490,7 +491,7 @@
// 1 bandgap
// 1 power-on-reset (POR)
// 1 temperature alarm
-
+
// NOTE: Signals affecting critical core functions are controlled through
// an independent SPI having read-only access through the picorv32 core.
// SPI pins are independent of picorv32 SPI master. Signals controlled by
@@ -522,7 +523,7 @@
// SPI slave: 0x030000c0 (read-only)
// Memory map details:
- // GPIO: 32 channels total.
+ // GPIO: 32 channels total.
// addr 0x03000000 data (16 bits)
// addr 0x03000001 out (=1) or in (=0) (default 0)
// addr 0x03000002 pu (=1) or none (=0) (default 0)
@@ -748,6 +749,9 @@
);
endmodule
+`include "picorv32.v"
+`include "spimemio.v"
+`include "simpleuart.v"
// Implementation note:
// Replace the following two modules with wrappers for your SRAM cells.
@@ -826,3 +830,4 @@
assign gpio_mode0_pad = ~gpio_outenb;
endmodule
+
