### PDN Config. All units in micrometer (um)
## The values used in this config are for reference only and do not correspond to any specific foundry
## design name to be used in DEF
set ::design "ariane"

## DEF DBU 
set ::def_units "2000"

##Input DEF with macros packed
set ::FpOutDef "/projects/ssg/pj10000064_diphda/users/colhol01/openroad/TritonFPlan/test/ariane/floorplan.def"

#### input tech lef path
set ::techLef "/home/zf4_techdata/tsmc65/arm_nda/all_extracted_files/arm/tsmc/cln65lp/arm_tech/r2p0/lef/1p9m_6x2z/sc12_tech.lef"
 
#### input cell lef path
set ::cellLef [list \
/projects/ssg/pj10000064_diphda/users/colhol01/openroad/TritonFPlan/test/tsmc-65lp/merged.lef]

#### input flat lef path. FLAT LEF that contains physical views of all standard cells and macros in the design
# Ensure that the file ends with END LIBRARY 
set ::flatLef /projects/ssg/pj10000064_diphda/users/colhol01/openroad/TritonFPlan/test/tsmc-65lp/merged.lef

set ::macro_power_pins "VDDPE VDDCE"
set ::macro_ground_pins "VSSE"

#### placement SITE name from LEF
set ::site_name "sc12_cln65lp" 
set ::site_width 0.2 

# Floorplan information - core boundary coordinates, std. cell row height,
# minimum track pitch as defined in LEF
set ::core_area_llx "14.0000"
set ::core_area_lly "14.0000"
set ::core_area_urx "1663.800"
set ::core_area_ury "1331.600"
set ::die_area_llx "0"
set ::die_area_lly "0"
set ::die_area_urx "1677.8"
set ::die_area_ury "1345.6"
set ::row_height "2.4"

# Power nets
set ::power_nets "VDD"
set ::ground_nets "VSS"

set ::macro_blockage_layer_list "M1 M2 M3 M4" 

# Details from techlef (BEOL LEF)
set ::met_layer_list "M1 M2 M3 M4 M5 M6 M7 M8 M9"  ;#From M1 and upwards
set ::met_layer_dir  "hor ver hor ver hor ver hor ver hor"

# Ensure pitches will make the stripes fall on track
# Ensure offsets will make the stripes fall on track

pdn specify_grid stdcell [list \
    layers    "M1 M4 M7" \
    dir       "hor ver hor" \
    widths    "0.64 0.93 0.93" \
    pitches   "2.40 40.0 40.0" \
    loffset   "0 2 2" \
    boffset   "0 2 2" \
    connect   "{M1 M4} {M4 M7}" \
    vias      "VIA1_RULE_1 VIA2_RULE_1 VIA3_RULE_1 VIA4_RULE_1 VIA5_RULE_264 VIA6_RULE_18 VIA7_RULE_18 VIA8_RULE_1" \
]
pdn specify_grid macro [list \
    layers    "M6" \
    dir       "ver" \
    widths    "0.93" \
    pitches   "40" \
    loffset   2 \
    boffset   0 \
    min_pitch 0.2 \
    connect   "{M4_PIN_hor M6} {M6 M7}" \
    vias      "VIA1_RULE_1 VIA2_RULE_1 VIA3_RULE_1 VIA4_RULE_293 VIA5_RULE_360 VIA6_RULE_21 VIA7_RULE_18 VIA8_RULE_1" \
]

set ::halo 4

# Metal layer for rails on every row
set ::rails_mlayer "M1" ;

# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
set ::rails_start_with "GROUND" ;

# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
set ::stripes_start_with "GROUND" ;

proc generate_viarules {} {
   pdn def_out "\n\nVIAS 14 ;\n"

   pdn def_out "- VIA1_RULE_1 \n + VIARULE VIA1_RULE \n + CUTSIZE 200 200 \n + LAYERS M1 VIA1 M2 \n + CUTSPACING 260 260 \n + ENCLOSURE 140 80 140 80 \n + ROWCOL 1 4 \n ;"
   pdn def_out "- VIA2_RULE_1 \n + VIARULE VIA2_RULE \n + CUTSIZE 200 200 \n + LAYERS M2 VIA2 M3 \n + CUTSPACING 260 260 \n + ENCLOSURE 140 80 140 80 \n + ROWCOL 1 4 \n ;"
   pdn def_out "- VIA3_RULE_1 \n + VIARULE VIA3_RULE \n + CUTSIZE 200 200 \n + LAYERS M3 VIA3 M4 \n + CUTSPACING 260 260 \n + ENCLOSURE 140 80 140 80 \n + ROWCOL 1 4 \n ;"
  
   pdn def_out "- VIA4_RULE_1 \n + VIARULE VIA4_RULE \n + CUTSIZE 200 200 \n + LAYERS M4 VIA4 M5 \n + CUTSPACING 260 260 \n + ENCLOSURE 140 80 140 80 \n + ROWCOL 1 4 \n ;"
   pdn def_out "- VIA4_RULE_6 \n + VIARULE VIA4_RULE \n + CUTSIZE 200 200 \n + LAYERS M4 VIA4 M5 \n + CUTSPACING 260 260 \n + ENCLOSURE 140 20 140 20 \n + ROWCOL 1 4 \n ;"
   pdn def_out "- VIA4_RULE_293 \n + VIARULE VIA4_RULE \n + CUTSIZE 200 200 \n + LAYERS M4 VIA4 M5 \n + CUTSPACING 260 260 \n + ENCLOSURE 140 20 140 20 \n + ROWCOL 1 4 \n ;"
   pdn def_out "- VIA4_RULE_294 \n + VIARULE VIA4_RULE \n + CUTSIZE 200 200 \n + LAYERS M4 VIA4 M5 \n + CUTSPACING 260 260 \n + ENCLOSURE 60 100 60 100 \n + ROWCOL 4 1 \n ;"
  
   pdn def_out "- VIA5_RULE_275 \n + VIARULE VIA5_RULE \n + CUTSIZE 200 200 \n + LAYERS M5 VIA4 M6 \n + CUTSPACING 260 260 \n + ENCLOSURE 140 20 140 20 \n + ROWCOL 1 4 \n ;"
   pdn def_out "- VIA5_RULE_264 \n + VIARULE VIA5_RULE \n + CUTSIZE 200 200 \n + LAYERS M5 VIA5 M6 \n + CUTSPACING 260 260 \n + ENCLOSURE 140 80 140 80 \n + ROWCOL 1 4 \n ;"
   pdn def_out "- VIA5_RULE_360 \n + VIARULE VIA5_RULE \n + CUTSIZE 200 200 \n + LAYERS M5 VIA5 M6 \n + CUTSPACING 260 260 \n + ENCLOSURE 20 220 20 220 \n + ROWCOL 1 4 \n ;"

   pdn def_out "- VIA6_RULE_18 \n + VIARULE VIA6_RULE \n + CUTSIZE 200 200 \n + LAYERS M6 VIA6 M7 \n + CUTSPACING 260 260 \n + ENCLOSURE 140 220 140 220 \n + ROWCOL 2 2 \n ;"
   pdn def_out "- VIA6_RULE_21 \n + VIARULE VIA6_RULE \n + CUTSIZE 200 200 \n + LAYERS M6 VIA6 M7 \n + CUTSPACING 260 260 \n + ENCLOSURE 20 220 20 220 \n + ROWCOL 2 2 \n ;"

   pdn def_out "- VIA7_RULE_18 \n + VIARULE VIA7_RULE \n + CUTSIZE 720 720 \n + LAYERS M7 VIA7 M8 \n + CUTSPACING 1120 680 \n + ENCLOSURE 1040 140 1040 140 \n + ROWCOL 2 2 \n ;"
   pdn def_out "- VIA8_RULE_1 \n + VIARULE VIA8_RULE \n + CUTSIZE 720 720 \n + LAYERS M8 VIA8 M9 \n + CUTSPACING 680 1120 \n + ENCLOSURE 40 280 40 280 \n + ROWCOL 2 2 \n ;"
   pdn def_out "END VIAS"
}