diff --git a/designs/raven_soc/src/raven_soc.v b/designs/raven_soc/src/raven_soc.v
index b27c719..23b9ece 100644
--- a/designs/raven_soc/src/raven_soc.v
+++ b/designs/raven_soc/src/raven_soc.v
@@ -206,7 +206,7 @@
 	assign clk = (ext_clk_sel == 1'b1) ? ext_clk : pll_clk;
 
 	// ADC clock assignments
-	
+
 	assign adc0_clk = (adc0_clksrc == 2'b00) ? rcosc_in :
 			  (adc0_clksrc == 2'b01) ? spi_sck :
 			  (adc0_clksrc == 2'b10) ? xtal_in :
@@ -224,9 +224,9 @@
 	assign gpio_out[2] = (rcosc_output_dest == 2'b01) ? rcosc_in : gpio[2];
 	assign gpio_out[3] = (rcosc_output_dest == 2'b10) ? rcosc_in : gpio[3];
 	assign gpio_out[4] = (rcosc_output_dest == 2'b11) ? rcosc_in : gpio[4];
-	assign gpio_out[5] = (xtal_output_dest == 2'b01) ? xtal_in : gpio[5]; 
-	assign gpio_out[6] = (xtal_output_dest == 2'b10) ? xtal_in : gpio[6]; 
-	assign gpio_out[7] = (xtal_output_dest == 2'b11) ? xtal_in : gpio[7]; 
+	assign gpio_out[5] = (xtal_output_dest == 2'b01) ? xtal_in : gpio[5];
+	assign gpio_out[6] = (xtal_output_dest == 2'b10) ? xtal_in : gpio[6];
+	assign gpio_out[7] = (xtal_output_dest == 2'b11) ? xtal_in : gpio[7];
 	assign gpio_out[8] = (pll_output_dest == 2'b01) ? pll_clk : gpio[8];
 	assign gpio_out[9] = (pll_output_dest == 2'b10) ? pll_clk : gpio[9];
 	assign gpio_out[10] = (pll_output_dest == 2'b11) ? clk : gpio[10];
@@ -238,7 +238,7 @@
 
 	assign gpio_outenb[0] = (comp_output_dest == 2'b00)  ? gpio_oeb[0] : 1'b0;
 	assign gpio_outenb[1] = (comp_output_dest == 2'b00)  ? gpio_oeb[1] : 1'b0;
-	assign gpio_outenb[2] = (rcosc_output_dest == 2'b00) ? gpio_oeb[2] : 1'b0; 
+	assign gpio_outenb[2] = (rcosc_output_dest == 2'b00) ? gpio_oeb[2] : 1'b0;
 	assign gpio_outenb[3] = (rcosc_output_dest == 2'b00) ? gpio_oeb[3] : 1'b0;
 	assign gpio_outenb[4] = (rcosc_output_dest == 2'b00) ? gpio_oeb[4] : 1'b0;
 	assign gpio_outenb[5] = (xtal_output_dest == 2'b00)  ? gpio_oeb[5] : 1'b0;
@@ -255,7 +255,7 @@
 
 	assign gpio_pullup[0] = (comp_output_dest == 2'b00)  ? gpio_pu[0] : 1'b0;
 	assign gpio_pullup[1] = (comp_output_dest == 2'b00)  ? gpio_pu[1] : 1'b0;
-	assign gpio_pullup[2] = (rcosc_output_dest == 2'b00) ? gpio_pu[2] : 1'b0; 
+	assign gpio_pullup[2] = (rcosc_output_dest == 2'b00) ? gpio_pu[2] : 1'b0;
 	assign gpio_pullup[3] = (rcosc_output_dest == 2'b00) ? gpio_pu[3] : 1'b0;
 	assign gpio_pullup[4] = (rcosc_output_dest == 2'b00) ? gpio_pu[4] : 1'b0;
 	assign gpio_pullup[5] = (xtal_output_dest == 2'b00)  ? gpio_pu[5] : 1'b0;
@@ -272,7 +272,7 @@
 
 	assign gpio_pulldown[0] = (comp_output_dest == 2'b00)  ? gpio_pd[0] : 1'b0;
 	assign gpio_pulldown[1] = (comp_output_dest == 2'b00)  ? gpio_pd[1] : 1'b0;
-	assign gpio_pulldown[2] = (rcosc_output_dest == 2'b00) ? gpio_pd[2] : 1'b0; 
+	assign gpio_pulldown[2] = (rcosc_output_dest == 2'b00) ? gpio_pd[2] : 1'b0;
 	assign gpio_pulldown[3] = (rcosc_output_dest == 2'b00) ? gpio_pd[3] : 1'b0;
 	assign gpio_pulldown[4] = (rcosc_output_dest == 2'b00) ? gpio_pd[4] : 1'b0;
 	assign gpio_pulldown[5] = (xtal_output_dest == 2'b00)  ? gpio_pd[5] : 1'b0;
@@ -443,7 +443,7 @@
 	// 1 bandgap
 	// 1 power-on-reset (POR)
 	// 1 temperature alarm
-	
+
 	// NOTE: Signals affecting critical core functions are controlled through
 	// an independent SPI having read-only access through the picorv32 core.
 	// SPI pins are independent of picorv32 SPI master.  Signals controlled by
@@ -475,7 +475,7 @@
 	// SPI slave:	0x030000c0	(read-only)
 
 	// Memory map details:
-	// GPIO:	32 channels total.  
+	// GPIO:	32 channels total.
 	//		addr 0x03000000		data (16 bits)
 	//		addr 0x03000001		out (=1) or in (=0) (default 0)
 	//		addr 0x03000002		pu (=1) or none (=0) (default 0)
@@ -691,16 +691,16 @@
 		end
 	end
 
-`ifndef		SRAM_COMPILER	
+`ifndef		SRAM_COMPILER
 	raven_soc_mem #(.WORDS(MEM_WORDS)) picomem (
 		.clk(clk),
 		.ena(resetn),
 		.wen((mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS) ? mem_wstrb : 4'b0),
-		.addr(mem_addr[23:2]),
+		.addr(mem_addr),
 		.wdata(mem_wdata),
 		.rdata(ram_rdata)
 	);
-`endif	
+`endif
 
 endmodule
 
@@ -739,19 +739,21 @@
 	input clk,
 	input ena,
 	input [3:0] wen,
-	input [21:0] addr,
+	input [31:0] addr,
 	input [31:0] wdata,
 	output reg [31:0] rdata
 );
 
-	wire [31:0] rdata_w;
+	wire [63:0] rdata_w;
 
-	sram_16_256_8_scn4m_subm sram1 (.clk0(clk), .csb0(ena), .web0(wen[0]|wen[1]), .wmask0(wen[1:0]), .addr0(addr[7:0]), .din0(wdata[7:0]), .dout0(rdata_w[15:0]));
-	sram_16_256_8_scn4m_subm sram2 (.clk0(clk), .csb0(ena), .web0(wen[2]|wen[3]), .wmask0(wen[3:2]), .addr0(addr[15:8]), .din0(wdata[15:8]), .dout0(rdata_w[31:16]));
+	sram_16_256_8_scn4m_subm sram1 (.clk0(clk), .csb0(ena), .web0(wen[0]), .wmask0({wen[0], wen[0]}), .addr0(addr[7:0]), .din0(wdata[7:0]), .dout0(rdata_w[15:0]));
+	sram_16_256_8_scn4m_subm sram2 (.clk0(clk), .csb0(ena), .web0(wen[1]), .wmask0({wen[1], wen[1]}), .addr0(addr[15:8]), .din0(wdata[15:8]), .dout0(rdata_w[31:16]));
+	sram_16_256_8_scn4m_subm sram3 (.clk0(clk), .csb0(ena), .web0(wen[2]), .wmask0({wen[2], wen[2]}), .addr0(addr[23:16]), .din0(wdata[23:16]), .dout0(rdata_w[47:32]));
+	sram_16_256_8_scn4m_subm sram4 (.clk0(clk), .csb0(ena), .web0(wen[3]), .wmask0({wen[3], wen[3]}), .addr0(addr[31:24]), .din0(wdata[31:24]), .dout0(rdata_w[63:48]));
 
 	always @(posedge clk) begin
 		if (ena == 1'b1) begin
-			rdata <= rdata_w;
+			rdata <= wen[0]? rdata_w[31:0] : rdata_w[63:32];
 		end
 	end
 endmodule