
# User config
set ::env(DESIGN_NAME) striVe_spi

# Change if needed
set ::env(VERILOG_FILES) ./designs/striVe_spi_noshifters/src/striVe_spi.v

# Fill this
set ::env(CLOCK_PERIOD) "10"
set ::env(CLOCK_PORT) "SCK"

set ::env(CLOCK_NET) $::env(CLOCK_PORT)
#set ::env(PDN_CFG) ./designs/striVe_spi_noshifters/pdn.tcl
#set ::env(FP_CORE_MARGIN) 3.8
set ::env(RUN_MAGIC) 1

set ::env(FP_IO_VEXTEND) 2
set ::env(FP_IO_HEXTEND) 2
set ::env(FP_IO_VTHICKNESS_MULT) 2
set ::env(FP_IO_HTHICKNESS_MULT) 2