diff --git a/configuration/floorplan.tcl b/configuration/floorplan.tcl
index 57d49b7..1e68d89 100644
--- a/configuration/floorplan.tcl
+++ b/configuration/floorplan.tcl
@@ -2,6 +2,7 @@
 set ::env(FP_IO_VMETAL) 2
 set ::env(FP_IO_HMETAL) 3
 
+set ::env(FP_SIZING) relative
 set ::env(FP_CORE_UTIL) 50
 set ::env(FP_CORE_MARGIN) 5.52
 set ::env(FP_ASPECT_RATIO) 1
diff --git a/configuration/general.tcl b/configuration/general.tcl
index 34d57d3..f11aa93 100644
--- a/configuration/general.tcl
+++ b/configuration/general.tcl
@@ -1,5 +1,5 @@
 # default pdk 
-set ::env(PDK) "ef-skywater-s8/EFS8A/"
+set ::env(PDK) "EFS8A/"
 set ::env(PDK_VARIANT) "scs8hd"
 set ::env(PDK_ROOT) $::env(OPENLANE_ROOT)/pdks/
 set ::env(USE_GPIO_PADS) 0
diff --git a/designs/striVe_flat/config_mod_diearea.tcl b/designs/striVe_flat/config_mod_diearea.tcl
index 3ba90b9..babb440 100644
--- a/designs/striVe_flat/config_mod_diearea.tcl
+++ b/designs/striVe_flat/config_mod_diearea.tcl
@@ -10,9 +10,9 @@
 
 set ::env(RUN_SIMPLE_CTS) 0
 set ::env(FILL_INSERTION) 1
-set ::env(GLB_RT_LI1_ADJUSTMENT) 0.75
-set ::env(GLB_RT_MET1_ADJUSTMENT) 0.75
-set ::env(FP_CORE_MARGIN) 155
+set ::env(GLB_RT_LI1_ADJUSTMENT) 1.0
+set ::env(GLB_RT_MET1_ADJUSTMENT) 1.0
+set ::env(FP_CORE_MARGIN) 162
 set ::env(CLOCK_NET) "clk"
 #set ::env(SYNTH_TOP_LEVEL) 1
 set ::env(USE_GPIO_PADS) 1
diff --git a/designs/striVe_flat/toplevel_mod_diearea.tcl b/designs/striVe_flat/toplevel_mod_diearea.tcl
index 577b90b..18418e7 100644
--- a/designs/striVe_flat/toplevel_mod_diearea.tcl
+++ b/designs/striVe_flat/toplevel_mod_diearea.tcl
@@ -34,5 +34,7 @@
 run_placement
 gen_pdn
 move_pins -from $pinsonly -to $::env(CURRENT_DEF)
+exec python3 $::env(SCRIPTS_DIR)/zeroize_origin_def.py < $::env(CURRENT_DEF) > $::env(CURRENT_DEF).zeroized
+exec mv $::env(CURRENT_DEF).zeroized $::env(CURRENT_DEF)
 run_routing
 #run_magic
diff --git a/docker_build/Makefile b/docker_build/Makefile
index 5b5a108..aec5207 100644
--- a/docker_build/Makefile
+++ b/docker_build/Makefile
@@ -3,7 +3,7 @@
 #ROOT = sudo
 
 #TOOLS = brown_yosys tapcell replace magic cts ioplacer pdn opendp resizer route macroplacer fastroute opensta yosys
-TOOLS = replace ioplacer opendp route fastroute opensta yosys tapcell magic resizer addspacers openroad_flow padring
+TOOLS = replace ioplacer opendp route fastroute opensta yosys tapcell magic resizer addspacers openroad_flow padring netgen vlogtoverilog
 
 TOOL_BUILD_TARGETS = $(foreach tool,$(TOOLS),build-$(tool))
 TOOL_EXPORT_TARGETS_PHONY = $(foreach tool,$(TOOLS),export-$(tool))
diff --git a/docker_build/docker/netgen/Dockerfile b/docker_build/docker/netgen/Dockerfile
new file mode 100644
index 0000000..b987f77
--- /dev/null
+++ b/docker_build/docker/netgen/Dockerfile
@@ -0,0 +1,35 @@
+# syntax = docker/dockerfile:1.0-experimental
+FROM centos:centos6 as build
+
+# Common development tools and libraries (kitchen sink approach)
+RUN yum groupinstall -y "Development Tools" "Development Libraries"
+RUN yum -y install centos-release-scl && \
+    yum -y install devtoolset-8 devtoolset-8-libatomic-devel
+
+ENV CC=/opt/rh/devtoolset-8/root/usr/bin/gcc \
+    CPP=/opt/rh/devtoolset-8/root/usr/bin/cpp \
+    CXX="/opt/rh/devtoolset-8/root/usr/bin/g++" \
+    PATH=/opt/rh/devtoolset-8/root/usr/bin:$PATH \
+    LD_LIBRARY_PATH=/opt/rh/devtoolset-8/root/usr/lib64:/opt/rh/devtoolset-8/root/usr/lib:/opt/rh/devtoolset-8/root/usr/lib64/dyninst:/opt/rh/devtoolset-8/root/usr/lib/dyninst:/opt/rh/devtoolset-8/root/usr/lib64:/opt/rh/devtoolset-8/root/usr/lib:$LD_LIBRARY_PATH
+#
+
+# netgen dependencies
+RUN yum install -y csh wget tcl-devel tk-devel libX11-devel cairo-devel ncurses-devel
+
+# git clone netgen components
+RUN git clone https://github.com/RTimothyEdwards/netgen
+
+WORKDIR "netgen"
+
+
+# build
+RUN ./configure --prefix=/build && \
+    make -j4 && \
+    make install
+
+RUN mkdir -p /build/version/
+
+RUN date +"Build Timestamp: %Y-%m-%d_%H-%M-%S" > /build/version/netgen.version
+RUN git rev-parse HEAD >> /build/version/netgen.version
+RUN tar -czf /build.tar.gz /build
+
diff --git a/docker_build/docker/vlogtoverilog/Dockerfile b/docker_build/docker/vlogtoverilog/Dockerfile
new file mode 100644
index 0000000..45e896d
--- /dev/null
+++ b/docker_build/docker/vlogtoverilog/Dockerfile
@@ -0,0 +1,29 @@
+# syntax = docker/dockerfile:1.0-experimental
+FROM centos:centos6 as build
+
+# install gcc 6
+RUN yum -y install centos-release-scl && \
+    yum -y install devtoolset-6 devtoolset-6-libatomic-devel
+ENV CC=/opt/rh/devtoolset-6/root/usr/bin/gcc \
+    CPP=/opt/rh/devtoolset-6/root/usr/bin/cpp \
+    CXX=/opt/rh/devtoolset-6/root/usr/bin/g++ \
+    PATH=/opt/rh/devtoolset-6/root/usr/bin:$PATH \
+    LD_LIBRARY_PATH=/opt/rh/devtoolset-6/root/usr/lib64:/opt/rh/devtoolset-6/root/usr/lib:/opt/rh/devtoolset-6/root/usr/lib64/dyninst:/opt/rh/devtoolset-6/root/usr/lib/dyninst:/opt/rh/devtoolset-6/root/usr/lib64:/opt/rh/devtoolset-6/root/usr/lib:$LD_LIBRARY_PATH
+
+RUN yum install -y git 
+RUN cd
+
+RUN git clone https://github.com/RTimothyEdwards/qflow
+
+WORKDIR qflow
+RUN git checkout a550469b63e910ede6e3022e2886bca96462c540
+
+RUN ./configure && cd src && make vlog2Verilog
+
+RUN mkdir -p /build/bin && cp /qflow/src/vlog2Verilog /build/bin/
+
+RUN mkdir -p /build/version/
+RUN date +"Build Timestamp: %Y-%m-%d_%H-%M-%S" > /build/version/vlog2Verilog.version
+RUN git rev-parse HEAD >> /build/version/vlog2Verilog.version
+RUN tar -czf /build.tar.gz /build
+
diff --git a/docker_build/tar/netgen.tar.gz b/docker_build/tar/netgen.tar.gz
new file mode 100644
index 0000000..478c21c
--- /dev/null
+++ b/docker_build/tar/netgen.tar.gz
Binary files differ
diff --git a/docker_build/tar/vlogtoverilog.tar.gz b/docker_build/tar/vlogtoverilog.tar.gz
new file mode 100644
index 0000000..da61a12
--- /dev/null
+++ b/docker_build/tar/vlogtoverilog.tar.gz
Binary files differ
diff --git a/flow.tcl b/flow.tcl
index f4c1dc7..10a861b 100755
--- a/flow.tcl
+++ b/flow.tcl
@@ -20,6 +20,8 @@
 	run_routing
 	run_magic	
 	run_magic_drc
+	run_magic_spice_export
+	run_netgen
 }
 
 proc run_interactive_mode {args} {
@@ -27,6 +29,40 @@
 	exec tclsh |& tee /dev/tty
 }
 
+proc run_magic_drc_batch {args} {
+	set options {{-magicrc optional} \
+			{-tech optional} \
+			{-report required} \
+			{-design required} \
+			{-gds required}}
+	set flags {}
+	parse_key_args "run_magic_drc_batch" args arg_values $options flags_mag $flags 
+	if { [info exists arg_values(-magicrc)] } {
+		set magicrc [file normalize $arg_values(-magicrc)]
+	}
+	if { [info exists arg_values(-tech)] } {
+		set ::env(TECH) [file normalize $arg_values(-tech)]
+	}
+	set ::env(GDS_INPUT) [file normalize $arg_values(-gds)]
+	set ::env(REPORT_OUTPUT) [file normalize $arg_values(-report)]
+	set ::env(DESIGN_NAME) $arg_values(-design)
+	
+	if { [info exists magicrc] } {
+		exec magic \
+			-noconsole \
+			-dnull \
+			-rcfile $magicrc \
+			$::env(OPENLANE_ROOT)/scripts/magic_drc_batch.tcl \
+			</dev/null |& tee /dev/tty
+	} else {
+		exec magic \
+			-noconsole \
+			-dnull \
+			$::env(OPENLANE_ROOT)/scripts/magic_drc_batch.tcl \
+			</dev/null |& /dev/tty
+	}
+}
+
 proc run_file {args} {
 	set ::env(TCLLIBPATH) $::env(OPENLANE_ROOT)/scripts/tcl_commands/
 	exec tclsh $args |& tee /dev/tty
@@ -39,7 +75,7 @@
 	}
 
 
-set flags {-init_design_config -disable_output -interactive}
+set flags {-init_design_config -disable_output -interactive -drc}
 
 set argv_copy $argv
 parse_key_args "flow.tcl" argv arg_values $options flags_map $flags
@@ -50,6 +86,8 @@
 	} else {
 		run_interactive_mode "$argv_copy"
 	}
+} elseif { [info exists flags_map(-drc)] } {
+	run_magic_drc_batch {*}$argv_copy
 } else {
 	run_non_interactive_mode {*}$argv_copy
 }
diff --git a/mykey.pub b/mykey.pub
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mykey.pub
diff --git a/pdks/EFS8A b/pdks/EFS8A
new file mode 120000
index 0000000..dedebb9
--- /dev/null
+++ b/pdks/EFS8A
@@ -0,0 +1 @@
+ef-skywater-s8/EFS8A
\ No newline at end of file
diff --git a/scripts/count_lvs.py b/scripts/count_lvs.py
new file mode 100755
index 0000000..0b5f23e
--- /dev/null
+++ b/scripts/count_lvs.py
@@ -0,0 +1,117 @@
+#!/usr/bin/python3
+#
+#---------------------------------------------------------
+# LVS failure check
+#
+# This is a Python script that parses the comp.json
+# output from netgen and reports on the number of
+# errors in the top-level netlist.
+#
+#---------------------------------------------------------
+# Written by Tim Edwards
+# efabless, inc.
+# Pulled from qflow GUI as standalone script Aug 20, 2018
+#---------------------------------------------------------
+
+import os
+import re
+import sys
+import json
+import argparse
+
+def count_LVS_failures(filename):
+    with open(filename, 'r') as cfile:
+        lvsdata = json.load(cfile)
+
+    # Count errors in the JSON file
+    failures = 0
+    devfail = 0
+    netfail = 0
+    pinfail = 0
+    propfail = 0
+    netdiff = 0
+    devdiff = 0
+    ncells = len(lvsdata)
+    for c in range(0, ncells):
+        cellrec = lvsdata[c]
+
+        if c == ncells - 1:
+            topcell = True
+        else:
+            topcell = False
+
+        # Most errors must only be counted for the top cell, because individual
+        # failing cells are flattened and the matching attempted again on the
+        # flattened netlist.
+
+        if topcell:
+            if 'devices' in cellrec:
+                devices = cellrec['devices']
+                devlist = [val for pair in zip(devices[0], devices[1]) for val in pair]
+                devpair = list(devlist[p:p + 2] for p in range(0, len(devlist), 2))
+                for dev in devpair:
+                    c1dev = dev[0]
+                    c2dev = dev[1]
+                    diffdevs = abs(c1dev[1] - c2dev[1])
+                    failures += diffdevs
+                    devdiff += diffdevs
+
+            if 'nets' in cellrec:
+                nets = cellrec['nets']
+                diffnets = abs(nets[0] - nets[1])
+                failures += diffnets
+                netdiff += diffnets
+
+            if 'badnets' in cellrec:
+                badnets = cellrec['badnets']
+                failures += len(badnets)
+                netfail += len(badnets)
+
+            if 'badelements' in cellrec:
+                badelements = cellrec['badelements']
+                failures += len(badelements)
+                devfail += len(badelements)
+
+            if 'pins' in cellrec:
+                pins = cellrec['pins']
+                pinlist = [val for pair in zip(pins[0], pins[1]) for val in pair]
+                pinpair = list(pinlist[p:p + 2] for p in range(0, len(pinlist), 2))
+                for pin in pinpair:
+                    # Avoid flagging global vs. local names, e.g., "gnd" vs. "gnd!,"
+                    # and ignore case when comparing pins.
+                    pin0 = re.sub('!$', '', pin[0].lower())
+                    pin1 = re.sub('!$', '', pin[1].lower())
+                    if pin0 != pin1:
+                        failures += 1
+                        pinfail += 1
+
+        # Property errors must be counted for every cell
+        if 'properties' in cellrec:
+            properties = cellrec['properties']
+            failures += len(properties)
+            propfail += len(properties)
+
+    return [failures, netfail, devfail, pinfail, propfail, netdiff, devdiff]
+
+if __name__ == '__main__':
+
+    parser = argparse.ArgumentParser(description='Parses netgen lvs')
+    parser.add_argument('--file', '-f', required=True)
+    args = parser.parse_args()
+    failures = count_LVS_failures(args.file)
+    total = failures[0]
+    if total > 0:
+        failed = True
+        print('LVS reports:')
+        print('    net count difference = ' + str(failures[5]))
+        print('    device count difference = ' + str(failures[6]))
+        print('    unmatched nets = ' + str(failures[1]))
+        print('    unmatched devices = ' + str(failures[2]))
+        print('    unmatched pins = ' + str(failures[3]))
+        print('    property failures = ' + str(failures[4]))
+    else:
+        print('LVS reports no net, device, pin, or property mismatches.')
+
+    print('')
+    print('Total errors = ' + str(total))
+ 
diff --git a/scripts/fastroute.tcl b/scripts/fastroute.tcl
index 7e3d8fe..4d3c4b6 100644
--- a/scripts/fastroute.tcl
+++ b/scripts/fastroute.tcl
@@ -6,6 +6,10 @@
 set_max_layer ${GLB_RT_MAXLAYER}
 set_layer_adjustment 1 ${GLB_RT_LI1_ADJUSTMENT}
 set_layer_adjustment 2 ${GLB_RT_MET1_ADJUSTMENT}
+set_unidirectional_routing false
+set_pitches_in_tile 10
+
+
 start_fastroute
 run_fastroute
 write_guides
diff --git a/scripts/magic_drc_batch.tcl b/scripts/magic_drc_batch.tcl
new file mode 100644
index 0000000..ca00086
--- /dev/null
+++ b/scripts/magic_drc_batch.tcl
@@ -0,0 +1,60 @@
+if { [info exists ::env(TECH)] } {
+	tech load $::env(TECH)
+}
+
+gds read $::env(GDS_INPUT)
+proc custom_drc_save_report {{cellname ""} {outfile ""}} {
+
+    if {$outfile == ""} {set outfile "drc.out"}
+
+    set fout [open $outfile w]
+    set oscale [cif scale out]
+
+    # magic::suspendall
+
+    if {$cellname == ""} {
+	select top cell
+        set cellname [cellname list self]
+	set origname ""
+    } else {
+	set origname [cellname list self]
+	puts stdout "loading $cellname\n"
+	flush stdout
+   
+	load $cellname
+	select top cell
+    }
+
+    drc check
+    set count [drc list count]
+
+    puts $fout "$cellname count: $count"
+    puts $fout "----------------------------------------"
+    set drcresult [drc listall why]
+    foreach {errtype coordlist} $drcresult {
+	puts $fout $errtype
+	puts $fout "----------------------------------------"
+	foreach coord $coordlist {
+	    set bllx [expr {$oscale * [lindex $coord 0]}]
+	    set blly [expr {$oscale * [lindex $coord 1]}]
+	    set burx [expr {$oscale * [lindex $coord 2]}]
+	    set bury [expr {$oscale * [lindex $coord 3]}]
+	    set coords [format " %.3f %.3f %.3f %.3f" $bllx $blly $burx $bury]
+	    puts $fout "$coords"
+	}
+	puts $fout "----------------------------------------"
+    }
+    puts $fout ""
+
+    if {$origname != ""} {
+	load $origname
+    }
+
+    # magic::resumeall
+
+    close $fout
+    puts "done with $outfile\n"
+    #flush stdout
+}
+
+custom_drc_save_report $::env(DESIGN_NAME) $::env(REPORT_OUTPUT)
diff --git a/scripts/tcl_commands/all.tcl b/scripts/tcl_commands/all.tcl
index dff8f5f..f4de39b 100644
--- a/scripts/tcl_commands/all.tcl
+++ b/scripts/tcl_commands/all.tcl
@@ -127,6 +127,7 @@
 		{tritonRoute routing/tritonRoute}
 		{magic magic/magic}
 		{cts cts/cts}
+		{lvs lvs/lvs}
 	}
 
 	set final_output \
@@ -137,6 +138,7 @@
 			[list tritonRoute routing/$::env(DESIGN_NAME).routing] \
 			[list cts cts/$::env(DESIGN_NAME).cts] \
 			[list magic magic/$::env(DESIGN_NAME).magic] \
+			[list lvs lvs/$::env(DESIGN_NAME).lvs] \
 		]
 
 	array set results_file_name [make_array $final_output $::env(RESULTS_DIR)]
@@ -158,11 +160,11 @@
 	}
 
 
-	try_catch mkdir -p $::env(RESULTS_DIR) $::env(TMP_DIR) $::env(LOG_DIR) $::env(REPORTS_DIR)
+	exec mkdir -p $::env(RESULTS_DIR) $::env(TMP_DIR) $::env(LOG_DIR) $::env(REPORTS_DIR)
 
-	set stages {synthesis floorplan placement cts routing magic}
+	set stages {synthesis floorplan placement cts routing magic lvs}
 	foreach stage $stages {
-		try_catch mkdir -p $::env(RESULTS_DIR)/$stage \
+		exec mkdir -p $::env(RESULTS_DIR)/$stage \
 			$::env(TMP_DIR)/$stage  \
 			$::env(LOG_DIR)/$stage \
 			$::env(REPORTS_DIR)/$stage
@@ -237,7 +239,6 @@
 	set_log ::env(LIB_MAX) $::env(LIB_MAX) $::env(GLB_CFG_FILE) 1
 	set_log ::env(LIB_TYPICAL) $::env(LIB_TYPICAL) $::env(GLB_CFG_FILE) 1
 	if { $::env(SYNTH_TOP_LEVEL) } {
-
 	set_log ::env(SYNTH_SCRIPT) "$::env(OPENLANE_ROOT)/scripts/synth_top.tcl" $::env(GLB_CFG_FILE) 0
 	} else {
 	set_log ::env(SYNTH_SCRIPT) "$::env(OPENLANE_ROOT)/scripts/synth.tcl" $::env(GLB_CFG_FILE) 0
@@ -248,7 +249,7 @@
 
 	# Floorplan
 	exec echo "# Floorplan config" >> $::env(GLB_CFG_FILE)
-	set_log ::env(FP_SIZING) "relative" $::env(GLB_CFG_FILE) 0; # absolute, relative
+	set_log ::env(FP_SIZING) $::env(FP_SIZING) $::env(GLB_CFG_FILE) 0; # absolute, relative
 	set_log ::env(FP_CORE_UTIL) $util $::env(GLB_CFG_FILE) 1
 	set_log ::env(FP_ASPECT_RATIO) $::env(FP_ASPECT_RATIO) $::env(GLB_CFG_FILE) 1
 	set_log ::env(FP_CORE_MARGIN) $::env(FP_CORE_MARGIN) $::env(GLB_CFG_FILE) 1
diff --git a/scripts/tcl_commands/lvs.tcl b/scripts/tcl_commands/lvs.tcl
new file mode 100644
index 0000000..a2165a8
--- /dev/null
+++ b/scripts/tcl_commands/lvs.tcl
@@ -0,0 +1,42 @@
+proc verilog_to_verilogPower {args} {
+	set options {{-input required} \
+			{-output required} \
+			{-lef required} \
+			{-power required} \
+			{-ground required}}
+	set flags {}
+	parse_key_args "verilog_to_verilogPower" args arg_values $options flags_map $flags
+	set bin vlog2Verilog
+	set in $arg_values(-input)
+	set out $arg_values(-output)
+	set power $arg_values(-power)
+	set gnd $arg_values(-ground)
+	set lef $arg_values(-lef)
+
+	try_catch $bin \
+		-v $power \
+		-g $gnd \
+		-l $lef \
+		$in |& tee $out
+}
+proc run_netgen {args} {
+	set ::env(NETGEN_SETUP_FILE) $::env(PDK_ROOT)/$::env(PDK)/libs.tech/netgen/$::env(PDK)_tech.lef ; # this should be definied in the pdk it's a tmp placeholder
+	set spice_in $::env(magic_result_file_tag).spice
+	set module_name $::env(DESIGN_NAME)
+	set verilog_in $::env(lvs_result_file_tag).v
+	set setup_file $::env(NETGEN_SETUP_FILE)
+	set output $::env(lvs_result_file_tag).log
+	verilog_to_verilogPower -input $::env(yosys_result_file_tag).v -output $verilog_in -lef $::env(MERGED_LEF) \
+		-power $::env(VDD_PIN) -ground $::env(GND_PIN)
+	exec netgen -batch lvs \
+		"$spice_in $module_name" \
+		"$verilog_in $module_name" \
+		$setup_file \
+		$output \
+		-json |& tee $::env(TERMINAL_OUTPUT) $::env(lvs_log_file_tag).log
+	exec python3 $::env(SCRIPTS_DIR)/count_lvs.py -f $::env(lvs_result_file_tag).json \
+		|& tee $::env(TERMINAL_OUTPUT) $::env(lvs_result_file_tag)_parsed.log
+	
+}
+
+package provide openlane 0.9
diff --git a/scripts/tcl_commands/magic.tcl b/scripts/tcl_commands/magic.tcl
new file mode 100644
index 0000000..24aa0f3
--- /dev/null
+++ b/scripts/tcl_commands/magic.tcl
@@ -0,0 +1,29 @@
+proc run_magic_spice_export {args} {
+	set magic_export $::env(TMP_DIR)/magic_spice.tcl
+set commands \
+"
+def read $::env(CURRENT_DEF)
+cd $::env(RESULTS_DIR)/magic/
+select top cell
+extract cell $::env(DESIGN_NAME)
+ext2spice lvs 
+ext2spice
+exec cp $::env(DESIGN_NAME).spice $::env(magic_result_file_tag).spice
+"
+	set magic_export_file [open $magic_export w]
+		puts $magic_export_file $commands
+	close $magic_export_file
+	set magicrc $::env(TMP_DIR)/magic.magicrc
+	set ::env(PDKPATH) "$::env(PDK_ROOT)/$::env(PDK)/"
+	set ::env(MAGPATH) "$::env(PDKPATH)/libs.ref/maglef"
+	exec envsubst < $::env(SCRIPTS_DIR)/tmp.magicrc > $magicrc
+	exec magic \
+		-noconsole \
+		-dnull \
+		-rcfile $magicrc \
+		$magic_export \
+		</dev/null \
+		|& tee $::env(TERMINAL_OUTPUT) $::env(magic_log_file_tag)_spice.log
+
+}
+package provide openlane 0.9
diff --git a/scripts/tcl_commands/pkgIndex.tcl b/scripts/tcl_commands/pkgIndex.tcl
index 4221bdd..d3653db 100755
--- a/scripts/tcl_commands/pkgIndex.tcl
+++ b/scripts/tcl_commands/pkgIndex.tcl
@@ -8,4 +8,4 @@
 # script is sourced, the variable $dir must contain the
 # full path name of this file's directory.
 
-package ifneeded openlane 0.9 [list source [file join $dir all.tcl]]\n[list source [file join $dir placement.tcl]]\n[list source [file join $dir init_design.tcl]]\n[list source [file join $dir floorplan.tcl]]\n[list source [file join $dir routing.tcl]]\n[list source [file join $dir cts.tcl]]\n[list source [file join $dir synthesis.tcl]]
+package ifneeded openlane 0.9 [list source [file join $dir lvs.tcl]]\n [file join $dir magic.tcl]]\n[file join $dir all.tcl]]\n[list source [file join $dir placement.tcl]]\n[list source [file join $dir init_design.tcl]]\n[list source [file join $dir floorplan.tcl]]\n[list source [file join $dir routing.tcl]]\n[list source [file join $dir cts.tcl]]\n[list source [file join $dir synthesis.tcl]]
diff --git a/scripts/utils/utils.tcl b/scripts/utils/utils.tcl
index bf61b09..6e169fe 100644
--- a/scripts/utils/utils.tcl
+++ b/scripts/utils/utils.tcl
@@ -82,7 +82,11 @@
 
 # a minimal try catch block
 proc try_catch {args} {
-	puts "Executing \"$args\"\n"
+	set cmd_log_file [open $::env(RUN_DIR)/cmds.log a+]
+	set timestamp [clock format [clock seconds]]
+	puts $cmd_log_file "$timestamp - Executing \"$args\"\n"
+	close $cmd_log_file
+
         if { [catch {eval exec $args} error_msg] } { 
 		set tool [string range $args 0 [string first " " $args]]
                 set print_error_msg "\[ERROR\]: during executing: \"$args\"\n"
diff --git a/succeed.tcl b/succeed.tcl
new file mode 100644
index 0000000..1504a69
--- /dev/null
+++ b/succeed.tcl
@@ -0,0 +1,3 @@
+verilog2def -verilog /home/ahmedg/openlane_dev/designs/spm/runs/abs_fp/results/synthesis/spm.synthesis.v -lef /home/ahmedg/openlane_dev/designs/spm/runs/abs_fp/tmp//merged.lef -liberty /home/ahmedg/openlane_dev/designs/spm/runs/abs_fp/tmp//trimmed.lib -top_module spm -site unitehd -tracks /home/ahmedg/openlane_dev/pdks//ef-skywater-s8/EFS8A//libs.tech/openlane/common_tracks.info -units 1000 -utilization 50 -aspect_ratio 1 -core_space 3.36 -def /home/ahmedg/openlane_dev/designs/spm/runs/abs_fp/tmp/floorplan/verilog2def_broken.def -verbose 
+
+