Merge branch 'develop_newscl' into develop
diff --git a/.gitmodules b/.gitmodules
index 5144d93..1fd508b 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,4 +1,3 @@
[submodule "pdks/ef-skywater-s8"]
path = pdks/ef-skywater-s8
url = git@gitlab.com:efabless/ef-pdk/ef-skywater-s8.git
- branch = dev
diff --git a/README.md b/README.md
index e8d5594..a8592f4 100644
--- a/README.md
+++ b/README.md
@@ -3,7 +3,7 @@
| || o ) [_ | _ || | | o || _ | / [_
| O || _/ _]| | || |___ | || | || _]
| || | | [_ | | || || _ || | || [_
- \___/ |__| |_____||__|__||_____||__|__||__|__||_____| ver 0.95
+ \___/ |__| |_____||__|__||_____||__|__||__|__||_____| ver 0.981
## Table of contents
diff --git a/configuration/floorplan.tcl b/configuration/floorplan.tcl
index 6a4fc1a..1e68d89 100644
--- a/configuration/floorplan.tcl
+++ b/configuration/floorplan.tcl
@@ -4,7 +4,7 @@
set ::env(FP_SIZING) relative
set ::env(FP_CORE_UTIL) 50
-set ::env(FP_CORE_MARGIN) 3.36
+set ::env(FP_CORE_MARGIN) 5.52
set ::env(FP_ASPECT_RATIO) 1
set ::env(FP_PDN_VOFFSET) 16.32
@@ -12,7 +12,7 @@
set ::env(FP_PDN_HOFFSET) 16.65
set ::env(FP_PDN_HPITCH) 153.18
-set ::env(FP_IO_VEXTEND) -1
-set ::env(FP_IO_HEXTEND) -1
-set ::env(FP_IO_VTHICKNESS_MULT) 1
-set ::env(FP_IO_HTHICKNESS_MULT) 1
+set ::env(FP_IO_VEXTEND) 2
+set ::env(FP_IO_HEXTEND) 2
+set ::env(FP_IO_VTHICKNESS_MULT) 2
+set ::env(FP_IO_HTHICKNESS_MULT) 2
diff --git a/configuration/general.tcl b/configuration/general.tcl
index 6f5a56c..f11aa93 100644
--- a/configuration/general.tcl
+++ b/configuration/general.tcl
@@ -1,6 +1,6 @@
# default pdk
set ::env(PDK) "EFS8A/"
-set ::env(PDK_VARIANT) "efs8hd"
+set ::env(PDK_VARIANT) "scs8hd"
set ::env(PDK_ROOT) $::env(OPENLANE_ROOT)/pdks/
set ::env(USE_GPIO_PADS) 0
diff --git a/configuration/routing.tcl b/configuration/routing.tcl
index e5ef760..327f57c 100644
--- a/configuration/routing.tcl
+++ b/configuration/routing.tcl
@@ -1,7 +1,7 @@
# Routing defaults
set ::env(GLB_RT_OLD_FR) 0
set ::env(GLB_RT_ADJUSTMENT) 0.15
-set ::env(GLB_RT_LI1_ADJUSTMENT) 0
+set ::env(GLB_RT_LI1_ADJUSTMENT) 0.85
set ::env(GLB_RT_MET1_ADJUSTMENT) 0
set ::env(GLB_RT_MINLAYER) 1
set ::env(GLB_RT_MAXLAYER) 6
diff --git a/designs/digital_pll/src/cells.v b/designs/digital_pll/src/cells.v
index b84aa50..1b6b0bd 100644
--- a/designs/digital_pll/src/cells.v
+++ b/designs/digital_pll/src/cells.v
@@ -1,32 +1,32 @@
(* blackbox *)
-module efs8hd_dfrbp_2 (output QN, input D, input CLK, output Q, input RESETB); endmodule
+module scs8hd_dfrbp_1 (output QN, input D, input CLK, output Q, input RESETB); endmodule
(* blackbox *)
-module efs8hd_inv_4 (input A, output Y); endmodule
+module scs8hd_inv_4 (input A, output Y); endmodule
(* blackbox *)
-module efs8hd_buf_1(input A, output X); endmodule
+module scs8hd_buf_1(input A, output X); endmodule
(* blackbox *)
-module efs8hd_clkbuf_1(input A, output X); endmodule
+module scs8hd_clkbuf_1(input A, output X); endmodule
(* blackbox *)
-module efs8hd_clkbuf_2(input A, output X); endmodule
+module scs8hd_clkbuf_2(input A, output X); endmodule
(* blackbox *)
-module efs8hd_clkinv_1(input A, output Y); endmodule
+module scs8hd_clkinv_1(input A, output Y); endmodule
(* blackbox *)
-module efs8hd_clkinv_2(input A, output Y); endmodule
+module scs8hd_clkinv_2(input A, output Y); endmodule
(* blackbox *)
-module efs8hd_clkinv_4(input A, output Y); endmodule
+module scs8hd_clkinv_4(input A, output Y); endmodule
(* blackbox *)
-module efs8hd_clkinv_8(input A, output Y); endmodule
+module scs8hd_clkinv_8(input A, output Y); endmodule
(* blackbox *)
-module efs8hd_conb_1(output HI, output LO); endmodule
+module scs8hd_conb_1(output HI, output LO); endmodule
(* blackbox *)
-module efs8hd_dfbbp_1(input CLK, input D, output Q, output QN, input RESETB, input SETB); endmodule
+module scs8hd_dfbbp_1(input CLK, input D, output Q, output QN, input RESETB, input SETB); endmodule
(* blackbox *)
-module efs8hd_einvn_4(input A, input TEB, output Z); endmodule
+module scs8hd_einvn_4(input A, input TEB, output Z); endmodule
(* blackbox *)
-module efs8hd_einvn_8(input A, input TEB, output Z); endmodule
+module scs8hd_einvn_8(input A, input TEB, output Z); endmodule
(* blackbox *)
-module efs8hd_einvp_1(input A, input TE, output Z); endmodule
+module scs8hd_einvp_1(input A, input TE, output Z); endmodule
(* blackbox *)
-module efs8hd_einvp_2(input A, input TE, output Z); endmodule
+module scs8hd_einvp_2(input A, input TE, output Z); endmodule
(* blackbox *)
-module efs8hd_or2_2(input A, B, output X); endmodule
+module scs8hd_or2_2(input A, B, output X); endmodule
diff --git a/designs/digital_pll/src/digital_pll.v b/designs/digital_pll/src/digital_pll.v
index 75d46b6..ca249af 100644
--- a/designs/digital_pll/src/digital_pll.v
+++ b/designs/digital_pll/src/digital_pll.v
@@ -34,7 +34,7 @@
// Derive negative-sense reset from the input positive-sense reset
- efs8hd_inv_4 irb (
+ scs8hd_inv_4 irb (
.A(reset),
.Y(resetb)
);
@@ -42,8 +42,8 @@
// Create divided down clocks. The inverted output only comes
// with digital standard cells with inverted resets, so the
// reset has to be inverted as well.
-
- efs8hd_dfrbp_2 idiv2 (
+
+ scs8hd_dfrbp_1 idiv2 (
.CLK(clockp[1]),
.D(clockd[0]),
.Q(nint[0]),
@@ -51,7 +51,7 @@
.RESETB(resetb)
);
- efs8hd_dfrbp_2 idiv4 (
+ scs8hd_dfrbp_1 idiv4 (
.CLK(clockd[0]),
.D(clockd[1]),
.Q(nint[1]),
@@ -59,7 +59,7 @@
.RESETB(resetb)
);
- efs8hd_dfrbp_2 idiv8 (
+ scs8hd_dfrbp_1 idiv8 (
.CLK(clockd[1]),
.D(clockd[2]),
.Q(nint[2]),
@@ -67,7 +67,7 @@
.RESETB(resetb)
);
- efs8hd_dfrbp_2 idiv16 (
+ scs8hd_dfrbp_1 idiv16 (
.CLK(clockd[2]),
.D(clockd[3]),
.Q(nint[3]),
diff --git a/designs/digital_pll/src/ring_osc2x13.v b/designs/digital_pll/src/ring_osc2x13.v
index eca5acf..bf405dd 100755
--- a/designs/digital_pll/src/ring_osc2x13.v
+++ b/designs/digital_pll/src/ring_osc2x13.v
@@ -10,40 +10,40 @@
wire d0, d1, d2;
- efs8hd_clkbuf_2 delaybuf0 (
+ scs8hd_clkbuf_2 delaybuf0 (
.A(in),
.X(ts)
);
- efs8hd_clkbuf_1 delaybuf1 (
+ scs8hd_clkbuf_1 delaybuf1 (
.A(ts),
.X(d0)
);
- efs8hd_einvp_2 delayen1 (
+ scs8hd_einvp_2 delayen1 (
.A(d0),
.TE(trim[1]),
.Z(d1)
);
- efs8hd_einvn_4 delayenb1 (
+ scs8hd_einvn_4 delayenb1 (
.A(ts),
.TEB(trim[1]),
.Z(d1)
);
- efs8hd_clkinv_1 delayint0 (
+ scs8hd_clkinv_1 delayint0 (
.A(d1),
.Y(d2)
);
- efs8hd_einvp_2 delayen0 (
+ scs8hd_einvp_2 delayen0 (
.A(d2),
.TE(trim[0]),
.Z(out)
);
- efs8hd_einvn_8 delayenb0 (
+ scs8hd_einvn_8 delayenb0 (
.A(ts),
.TEB(trim[0]),
.Z(out)
@@ -59,29 +59,29 @@
wire d0, d1, d2, ctrl0, one;
- efs8hd_clkbuf_1 delaybuf0 (
+ scs8hd_clkbuf_1 delaybuf0 (
.A(in),
.X(d0)
);
- efs8hd_einvp_2 delayen1 (
+ scs8hd_einvp_2 delayen1 (
.A(d0),
.TE(trim[1]),
.Z(d1)
);
- efs8hd_einvn_4 delayenb1 (
+ scs8hd_einvn_4 delayenb1 (
.A(in),
.TEB(trim[1]),
.Z(d1)
);
- efs8hd_clkinv_1 delayint0 (
+ scs8hd_clkinv_1 delayint0 (
.A(d1),
.Y(d2)
);
- efs8hd_einvp_2 delayen0 (
+ scs8hd_einvp_2 delayen0 (
.A(d2),
.TE(trim[0]),
.Z(out)
@@ -93,19 +93,19 @@
.Z(out)
);
- efs8hd_einvp_1 reseten0 (
+ scs8hd_einvp_1 reseten0 (
.A(one),
.TE(reset),
.Z(out)
);
- efs8hd_or2_2 ctrlen0 (
+ scs8hd_or2_2 ctrlen0 (
.A(reset),
.B(trim[0]),
.X(ctrl0)
);
- efs8hd_conb_1 const1 (
+ scs8hd_conb_1 const1 (
.HI(one),
.LO()
);
@@ -136,7 +136,7 @@
wire [1:0] c;
// Main oscillator loop stages
-
+
genvar i;
generate
for (i = 0; i < 12; i = i + 1) begin : dstage
@@ -149,7 +149,7 @@
endgenerate
// Reset/startup stage
-
+
start_stage iss (
.in(d[12]),
.trim({trim[25], trim[12]}),
@@ -159,19 +159,19 @@
// Buffered outputs a 0 and 90 degrees phase (approximately)
- efs8hd_clkinv_2 ibufp00 (
+ scs8hd_clkinv_2 ibufp00 (
.A(d[0]),
.Y(c[0])
);
- efs8hd_clkinv_8 ibufp01 (
+ scs8hd_clkinv_8 ibufp01 (
.A(c[0]),
.Y(clockp[0])
);
- efs8hd_clkinv_2 ibufp10 (
+ scs8hd_clkinv_2 ibufp10 (
.A(d[6]),
.Y(c[1])
);
- efs8hd_clkinv_8 ibufp11 (
+ scs8hd_clkinv_8 ibufp11 (
.A(c[1]),
.Y(clockp[1])
);
diff --git a/designs/openstriVe_soc/src/openstriVe_soc.v b/designs/openstriVe_soc/src/openstriVe_soc.v
deleted file mode 100644
index 1409be9..0000000
--- a/designs/openstriVe_soc/src/openstriVe_soc.v
+++ /dev/null
@@ -1,763 +0,0 @@
-/*
- * PicoSoC - A simple example SoC using PicoRV32
- *
- * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- * Revision 1, July 2019: Added signals to drive flash_clk and flash_csb
- * output enable (inverted), tied to reset so that the flash is completely
- * isolated from the processor when the processor is in reset.
- *
- * Also: Made ram_wenb a 4-bit bus so that the memory access can be made
- * byte-wide for byte-wide instructions.
- */
-
-`ifdef PICORV32_V
-`error "openstriVe_soc.v must be read before picorv32.v!"
-`endif
-
-/* Note: Synthesize register memory from flops */
-/* Inefficient, but not terribly so */
-
-/* Also note: To avoid having a hard macro in the place & route */
-/* (method not finished yet in qflow), SRAM pins are brought out to */
-/* the openstriVe_soc I/O so that openstriVe_soc.v itself is fully synthesizable */
-/* and routable with qflow as-is. */
-
-`define PICORV32_REGS openstriVe_soc_regs
-
-module openstriVe_soc (
-`ifdef LVS
- inout vdd1v8, /* 1.8V domain */
- inout vss,
-`endif
- input pll_clk,
- input ext_clk,
- input ext_clk_sel,
- input ext_reset,
- input reset,
-
- // Main SRAM, including clk and resetn above
- // (Not used: RAM is synthesized in this version)
- /*
- output [3:0] ram_wenb,
- output [9:0] ram_addr,
- output [31:0] ram_wdata,
- input [31:0] ram_rdata,
- */
-
- // Memory mapped I/O signals
- output [15:0] gpio_out, // Connect to out on gpio pad
- input [15:0] gpio_in, // Connect to in on gpio pad
- output [15:0] gpio_pullupb, // Connect to pullupb on gpio pad
- output [15:0] gpio_pulldownb, // Connect to pulldownb on gpio pad
- output [15:0] gpio_outenb, // Connect to outenb on gpio pad
-
- output adc0_ena,
- output adc0_convert,
- input [9:0] adc0_data,
- input adc0_done,
- output adc0_clk,
- output [1:0] adc0_inputsrc,
- output adc1_ena,
- output adc1_convert,
- output adc1_clk,
- output [1:0] adc1_inputsrc,
- input [9:0] adc1_data,
- input adc1_done,
-
- output dac_ena,
- output [9:0] dac_value,
-
- output analog_out_sel, // Analog output select (DAC or bandgap)
- output opamp_ena, // Op-amp enable for analog output
- output opamp_bias_ena, // Op-amp bias enable for analog output
- output bg_ena, // Bandgap enable
-
- output comp_ena,
- output [1:0] comp_ninputsrc,
- output [1:0] comp_pinputsrc,
- output rcosc_ena,
-
- output overtemp_ena,
- input overtemp,
- input rcosc_in, // RC oscillator output
- input xtal_in, // crystal oscillator output
- input comp_in, // comparator output
- input spi_sck,
-
- input [7:0] spi_ro_config,
- input spi_ro_xtal_ena,
- input spi_ro_reg_ena,
- input spi_ro_pll_cp_ena,
- input spi_ro_pll_vco_ena,
- input spi_ro_pll_bias_ena,
- input [3:0] spi_ro_pll_trim,
-
- input [11:0] spi_ro_mfgr_id,
- input [7:0] spi_ro_prod_id,
- input [3:0] spi_ro_mask_rev,
-
- output ser_tx,
- input ser_rx,
-
- // IRQ
- input irq_pin, // dedicated IRQ pin
- input irq_spi, // IRQ from standalone SPI
-
- // trap
- output trap,
-
- // Flash memory control (SPI master)
- output flash_csb,
- output flash_clk,
-
- output flash_csb_oeb,
- output flash_clk_oeb,
-
- output flash_io0_oeb,
- output flash_io1_oeb,
- output flash_io2_oeb,
- output flash_io3_oeb,
-
- output flash_io0_do,
- output flash_io1_do,
- output flash_io2_do,
- output flash_io3_do,
-
- input flash_io0_di,
- input flash_io1_di,
- input flash_io2_di,
- input flash_io3_di
-);
- /* parameter integer MEM_WORDS = 256; */
- /* Increase scratchpad memory to 1K words */
- parameter integer MEM_WORDS = 256;
- parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory
- parameter [31:0] PROGADDR_RESET = 32'h 0010_0000; // 1 MB into flash
-
- wire resetn;
- wire clk;
-
- wire iomem_valid;
- reg iomem_ready;
- wire [ 3:0] iomem_wstrb;
- wire [31:0] iomem_addr;
- wire [31:0] iomem_wdata;
- reg [31:0] iomem_rdata;
-
- // memory-mapped I/O control registers
-
- reg [15:0] gpio; // GPIO output data
- reg [15:0] gpio_pu; // GPIO pull-up enable
- reg [15:0] gpio_pd; // GPIO pull-down enable
- reg [15:0] gpio_oeb; // GPIO output enable (sense negative)
- reg adc0_ena; // ADC0 enable
- reg adc0_convert; // ADC0 convert
- reg [1:0] adc0_clksrc; // ADC0 clock source
- reg [1:0] adc0_inputsrc; // ADC0 input source
- reg adc1_ena; // ADC1 enable
- reg adc1_convert; // ADC1 convert
- reg [1:0] adc1_clksrc; // ADC1 clock source
- reg [1:0] adc1_inputsrc; // ADC1 input source
- reg dac_ena; // DAC enable
- reg [9:0] dac_value; // DAC output value
- reg comp_ena; // Comparator enable
- reg [1:0] comp_ninputsrc; // Comparator negative input source
- reg [1:0] comp_pinputsrc; // Comparator positive input source
- reg rcosc_ena; // RC oscillator enable
- reg overtemp_ena; // Over-temperature alarm enable
- reg [1:0] comp_output_dest; // Comparator output destination
- reg [1:0] rcosc_output_dest; // RC oscillator output destination
- reg [1:0] overtemp_dest; // Over-temperature alarm destination
- reg [1:0] pll_output_dest; // PLL clock output destination
- reg [1:0] xtal_output_dest; // Crystal oscillator output destination
- reg [1:0] trap_output_dest; // Trap signal output destination
- reg [1:0] irq_7_inputsrc; // IRQ 5 source
- reg [1:0] irq_8_inputsrc; // IRQ 6 source
- reg analog_out_sel; // Analog output select
- reg opamp_ena; // Analog output op-amp enable
- reg opamp_bias_ena; // Analog output op-amp bias enable
- reg bg_ena; // Bandgap enable
- wire adc0_clk; // ADC0 clock (multiplexed)
- wire adc1_clk; // ADC1 clock (multiplexed)
-
- wire [3:0] ram_wenb;
- wire [9:0] ram_addr;
- wire [31:0] ram_wdata;
-
- // Clock assignment (to do: make this glitch-free)
- assign clk = (ext_clk_sel == 1'b1) ? ext_clk : pll_clk;
-
- // Reset assignment. "reset" comes from POR, while "ext_reset"
- // comes from standalone SPI (and is normally zero unless
- // activated from the SPI).
-
- // Staged-delay reset
- reg [2:0] reset_delay;
-
- always @(posedge clk or posedge reset) begin
- if (reset == 1'b1) begin
- reset_delay <= 3'b111;
- end else begin
- reset_delay <= {1'b0, reset_delay[2:1]};
- end
- end
-
- assign resetn = ~(reset_delay[0] | ext_reset);
-
- // ADC clock assignments
-
- assign adc0_clk = (adc0_clksrc == 2'b00) ? rcosc_in :
- (adc0_clksrc == 2'b01) ? spi_sck :
- (adc0_clksrc == 2'b10) ? xtal_in :
- ext_clk;
-
- assign adc1_clk = (adc1_clksrc == 2'b00) ? rcosc_in :
- (adc1_clksrc == 2'b01) ? spi_sck :
- (adc1_clksrc == 2'b10) ? xtal_in :
- ext_clk;
-
- // GPIO assignments
-
- assign gpio_out[0] = (comp_output_dest == 2'b01) ? comp_in : gpio[0];
- assign gpio_out[1] = (comp_output_dest == 2'b10) ? comp_in : gpio[1];
- assign gpio_out[2] = (rcosc_output_dest == 2'b01) ? rcosc_in : gpio[2];
- assign gpio_out[3] = (rcosc_output_dest == 2'b10) ? rcosc_in : gpio[3];
- assign gpio_out[4] = (rcosc_output_dest == 2'b11) ? rcosc_in : gpio[4];
- assign gpio_out[5] = (xtal_output_dest == 2'b01) ? xtal_in : gpio[5];
- assign gpio_out[6] = (xtal_output_dest == 2'b10) ? xtal_in : gpio[6];
- assign gpio_out[7] = (xtal_output_dest == 2'b11) ? xtal_in : gpio[7];
- assign gpio_out[8] = (pll_output_dest == 2'b01) ? pll_clk : gpio[8];
- assign gpio_out[9] = (pll_output_dest == 2'b10) ? pll_clk : gpio[9];
- assign gpio_out[10] = (pll_output_dest == 2'b11) ? clk : gpio[10];
- assign gpio_out[11] = (trap_output_dest == 2'b01) ? trap : gpio[11];
- assign gpio_out[12] = (trap_output_dest == 2'b10) ? trap : gpio[12];
- assign gpio_out[13] = (trap_output_dest == 2'b11) ? trap : gpio[13];
- assign gpio_out[14] = (overtemp_dest == 2'b01) ? overtemp : gpio[14];
- assign gpio_out[15] = (overtemp_dest == 2'b10) ? overtemp : gpio[15];
-
- assign gpio_outenb[0] = (comp_output_dest == 2'b00) ? gpio_oeb[0] : 1'b0;
- assign gpio_outenb[1] = (comp_output_dest == 2'b00) ? gpio_oeb[1] : 1'b0;
- assign gpio_outenb[2] = (rcosc_output_dest == 2'b00) ? gpio_oeb[2] : 1'b0;
- assign gpio_outenb[3] = (rcosc_output_dest == 2'b00) ? gpio_oeb[3] : 1'b0;
- assign gpio_outenb[4] = (rcosc_output_dest == 2'b00) ? gpio_oeb[4] : 1'b0;
- assign gpio_outenb[5] = (xtal_output_dest == 2'b00) ? gpio_oeb[5] : 1'b0;
- assign gpio_outenb[6] = (xtal_output_dest == 2'b00) ? gpio_oeb[6] : 1'b0;
- assign gpio_outenb[7] = (xtal_output_dest == 2'b00) ? gpio_oeb[7] : 1'b0;
- assign gpio_outenb[8] = (pll_output_dest == 2'b00) ? gpio_oeb[8] : 1'b0;
- assign gpio_outenb[9] = (pll_output_dest == 2'b00) ? gpio_oeb[9] : 1'b0;
- assign gpio_outenb[10] = (pll_output_dest == 2'b00) ? gpio_oeb[10] : 1'b0;
- assign gpio_outenb[11] = (trap_output_dest == 2'b00) ? gpio_oeb[11] : 1'b0;
- assign gpio_outenb[12] = (trap_output_dest == 2'b00) ? gpio_oeb[12] : 1'b0;
- assign gpio_outenb[13] = (trap_output_dest == 2'b00) ? gpio_oeb[13] : 1'b0;
- assign gpio_outenb[14] = (overtemp_dest == 2'b00) ? gpio_oeb[14] : 1'b0;
- assign gpio_outenb[15] = (overtemp_dest == 2'b00) ? gpio_oeb[15] : 1'b0;
-
- assign gpio_pullupb[0] = (comp_output_dest == 2'b00) ? ~gpio_pu[0] : 1'b1;
- assign gpio_pullupb[1] = (comp_output_dest == 2'b00) ? ~gpio_pu[1] : 1'b1;
- assign gpio_pullupb[2] = (rcosc_output_dest == 2'b00) ? ~gpio_pu[2] : 1'b1;
- assign gpio_pullupb[3] = (rcosc_output_dest == 2'b00) ? ~gpio_pu[3] : 1'b1;
- assign gpio_pullupb[4] = (rcosc_output_dest == 2'b00) ? ~gpio_pu[4] : 1'b1;
- assign gpio_pullupb[5] = (xtal_output_dest == 2'b00) ? ~gpio_pu[5] : 1'b1;
- assign gpio_pullupb[6] = (xtal_output_dest == 2'b00) ? ~gpio_pu[6] : 1'b1;
- assign gpio_pullupb[7] = (xtal_output_dest == 2'b00) ? ~gpio_pu[7] : 1'b1;
- assign gpio_pullupb[8] = (pll_output_dest == 2'b00) ? ~gpio_pu[8] : 1'b1;
- assign gpio_pullupb[9] = (pll_output_dest == 2'b00) ? ~gpio_pu[9] : 1'b1;
- assign gpio_pullupb[10] = (pll_output_dest == 2'b00) ? ~gpio_pu[10] : 1'b1;
- assign gpio_pullupb[11] = (trap_output_dest == 2'b00) ? ~gpio_pu[11] : 1'b1;
- assign gpio_pullupb[12] = (trap_output_dest == 2'b00) ? ~gpio_pu[12] : 1'b1;
- assign gpio_pullupb[13] = (trap_output_dest == 2'b00) ? ~gpio_pu[13] : 1'b1;
- assign gpio_pullupb[14] = (overtemp_dest == 2'b00) ? ~gpio_pu[14] : 1'b1;
- assign gpio_pullupb[15] = (overtemp_dest == 2'b00) ? ~gpio_pu[15] : 1'b1;
-
- assign gpio_pulldownb[0] = (comp_output_dest == 2'b00) ? ~gpio_pd[0] : 1'b1;
- assign gpio_pulldownb[1] = (comp_output_dest == 2'b00) ? ~gpio_pd[1] : 1'b1;
- assign gpio_pulldownb[2] = (rcosc_output_dest == 2'b00) ? ~gpio_pd[2] : 1'b1;
- assign gpio_pulldownb[3] = (rcosc_output_dest == 2'b00) ? ~gpio_pd[3] : 1'b1;
- assign gpio_pulldownb[4] = (rcosc_output_dest == 2'b00) ? ~gpio_pd[4] : 1'b1;
- assign gpio_pulldownb[5] = (xtal_output_dest == 2'b00) ? ~gpio_pd[5] : 1'b1;
- assign gpio_pulldownb[6] = (xtal_output_dest == 2'b00) ? ~gpio_pd[6] : 1'b1;
- assign gpio_pulldownb[7] = (xtal_output_dest == 2'b00) ? ~gpio_pd[7] : 1'b1;
- assign gpio_pulldownb[8] = (pll_output_dest == 2'b00) ? ~gpio_pd[8] : 1'b1;
- assign gpio_pulldownb[9] = (pll_output_dest == 2'b00) ? ~gpio_pd[9] : 1'b1;
- assign gpio_pulldownb[10] = (pll_output_dest == 2'b00) ? ~gpio_pd[10] : 1'b1;
- assign gpio_pulldownb[11] = (trap_output_dest == 2'b00) ? ~gpio_pd[11] : 1'b1;
- assign gpio_pulldownb[12] = (trap_output_dest == 2'b00) ? ~gpio_pd[12] : 1'b1;
- assign gpio_pulldownb[13] = (trap_output_dest == 2'b00) ? ~gpio_pd[13] : 1'b1;
- assign gpio_pulldownb[14] = (overtemp_dest == 2'b00) ? ~gpio_pd[14] : 1'b1;
- assign gpio_pulldownb[15] = (overtemp_dest == 2'b00) ? ~gpio_pd[15] : 1'b1;
-
- wire irq_7, irq_8;
-
- assign irq_7 = (irq_7_inputsrc == 2'b01) ? gpio_in[0] :
- (irq_7_inputsrc == 2'b10) ? gpio_in[1] :
- (irq_7_inputsrc == 2'b11) ? gpio_in[2] : 1'b0;
- assign irq_8 = (irq_8_inputsrc == 2'b01) ? gpio_in[3] :
- (irq_8_inputsrc == 2'b10) ? gpio_in[4] :
- (irq_8_inputsrc == 2'b11) ? gpio_in[5] : 1'b0;
-
- assign ram_wenb = (mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS) ?
- {~mem_wstrb[3], ~mem_wstrb[2], ~mem_wstrb[1], ~mem_wstrb[0]} : 4'b1111;
- assign ram_addr = mem_addr[11:2];
- assign ram_wdata = mem_wdata; // Just for naming conventions.
-
- reg [31:0] irq;
- wire irq_stall = 0;
- wire irq_uart = 0;
-
- always @* begin
- irq = 0;
- irq[3] = irq_stall;
- irq[4] = irq_uart;
- irq[5] = irq_pin;
- irq[6] = irq_spi;
- irq[7] = irq_7;
- irq[8] = irq_8;
- irq[9] = comp_output_dest[0] & comp_output_dest[1] & comp_in;
- irq[10] = overtemp_dest[0] & overtemp_dest[1] & overtemp;
- end
-
- wire mem_valid;
- wire mem_instr;
- wire mem_ready;
- wire [31:0] mem_addr;
- wire [31:0] mem_wdata;
- wire [3:0] mem_wstrb;
- wire [31:0] mem_rdata;
-
- wire spimem_ready;
- wire [31:0] spimem_rdata;
-
- reg ram_ready;
- wire [31:0] ram_rdata;
-
- assign iomem_valid = mem_valid && (mem_addr[31:24] > 8'h 01);
- assign iomem_wstrb = mem_wstrb;
- assign iomem_addr = mem_addr;
- assign iomem_wdata = mem_wdata;
-
- wire spimemio_cfgreg_sel = mem_valid && (mem_addr == 32'h 0200_0000);
- wire [31:0] spimemio_cfgreg_do;
-
- wire simpleuart_reg_div_sel = mem_valid && (mem_addr == 32'h 0200_0004);
- wire [31:0] simpleuart_reg_div_do;
-
- wire simpleuart_reg_dat_sel = mem_valid && (mem_addr == 32'h 0200_0008);
- wire [31:0] simpleuart_reg_dat_do;
- wire simpleuart_reg_dat_wait;
-
- assign mem_ready = (iomem_valid && iomem_ready) || spimem_ready || ram_ready || spimemio_cfgreg_sel ||
- simpleuart_reg_div_sel || (simpleuart_reg_dat_sel && !simpleuart_reg_dat_wait);
-
- assign mem_rdata = (iomem_valid && iomem_ready) ? iomem_rdata : spimem_ready ? spimem_rdata : ram_ready ? ram_rdata :
- spimemio_cfgreg_sel ? spimemio_cfgreg_do : simpleuart_reg_div_sel ? simpleuart_reg_div_do :
- simpleuart_reg_dat_sel ? simpleuart_reg_dat_do : 32'h 0000_0000;
-
- picorv32 #(
- .STACKADDR(STACKADDR),
- .PROGADDR_RESET(PROGADDR_RESET),
- .PROGADDR_IRQ(32'h 0000_0000),
- .BARREL_SHIFTER(1),
- .COMPRESSED_ISA(1),
- .ENABLE_MUL(1),
- .ENABLE_DIV(1),
- .ENABLE_IRQ(1),
- .ENABLE_IRQ_QREGS(0)
- ) cpu (
- .clk (clk ),
- .resetn (resetn ),
- .mem_valid (mem_valid ),
- .mem_instr (mem_instr ),
- .mem_ready (mem_ready ),
- .mem_addr (mem_addr ),
- .mem_wdata (mem_wdata ),
- .mem_wstrb (mem_wstrb ),
- .mem_rdata (mem_rdata ),
- .irq (irq ),
- .trap (trap )
- );
-
- spimemio spimemio (
- .clk (clk),
- .resetn (resetn),
- .valid (mem_valid && mem_addr >= 4*MEM_WORDS && mem_addr < 32'h 0200_0000),
- .ready (spimem_ready),
- .addr (mem_addr[23:0]),
- .rdata (spimem_rdata),
-
- .flash_csb (flash_csb ),
- .flash_clk (flash_clk ),
-
- .flash_csb_oeb (flash_csb_oeb),
- .flash_clk_oeb (flash_clk_oeb),
-
- .flash_io0_oeb (flash_io0_oeb),
- .flash_io1_oeb (flash_io1_oeb),
- .flash_io2_oeb (flash_io2_oeb),
- .flash_io3_oeb (flash_io3_oeb),
-
- .flash_io0_do (flash_io0_do),
- .flash_io1_do (flash_io1_do),
- .flash_io2_do (flash_io2_do),
- .flash_io3_do (flash_io3_do),
-
- .flash_io0_di (flash_io0_di),
- .flash_io1_di (flash_io1_di),
- .flash_io2_di (flash_io2_di),
- .flash_io3_di (flash_io3_di),
-
- .cfgreg_we(spimemio_cfgreg_sel ? mem_wstrb : 4'b 0000),
- .cfgreg_di(mem_wdata),
- .cfgreg_do(spimemio_cfgreg_do)
- );
-
- simpleuart simpleuart (
- .clk (clk ),
- .resetn (resetn ),
-
- .ser_tx (ser_tx ),
- .ser_rx (ser_rx ),
-
- .reg_div_we (simpleuart_reg_div_sel ? mem_wstrb : 4'b 0000),
- .reg_div_di (mem_wdata),
- .reg_div_do (simpleuart_reg_div_do),
-
- .reg_dat_we (simpleuart_reg_dat_sel ? mem_wstrb[0] : 1'b 0),
- .reg_dat_re (simpleuart_reg_dat_sel && !mem_wstrb),
- .reg_dat_di (mem_wdata),
- .reg_dat_do (simpleuart_reg_dat_do),
- .reg_dat_wait(simpleuart_reg_dat_wait)
- );
-
- always @(posedge clk)
- ram_ready <= mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS;
-
- // PicoSoC memory mapped IP
- // 2 ADCs (1 multiplexed from internal signals, including core 1.8V VDD,
- // DAC output, comparator input, external input)
- // 1 DAC
- // 1 comparator (1 end tied to DAC, other could be shared w/ADC input)
- // 1 RC oscillator (output can be tied to one or both ADC clocks)
- // 1 crystal oscillator (output to level-shift-down = 3V buffer powered at 1.8V)
- // 1 1.8V regulator (sets VDD on padframe)
- // 1 bandgap
- // 1 power-on-reset (POR)
- // 1 temperature alarm
-
- // NOTE: Signals affecting critical core functions are controlled through
- // an independent SPI having read-only access through the picorv32 core.
- // SPI pins are independent of picorv32 SPI master. Signals controlled by
- // the SPI are:
- // 1) crystal oscillator enable (default on)
- // 2) 1.8V regulator enable (default on)
- // 3) bandgap enable (default on)
- // 4) picorv32 internal debug signals (TBD)
- // 5) additional picorv32 IRQ (TBD)
- // 6) PLL enables (default on)
- // 7) PLL trim (default TBD)
- // NOTE: SPI should have a pass-through mode that configures SDO as a
- // copy of a chosen signal for as long as CSB is held low. This can be
- // an SPI command, allows other internal signals to be passed to the
- // output and viewed, including the RC oscillator output, comparator output,
- // and other edge-based signals.
-
- // Memory map:
- // NOTE:
-
- // SPI master: 0x02000000 (control)
- // UART: 0x02000004-8 (clock, data)
- // GPIO: 0x03000000 (in/out, pu/pd, data)
- // ADC0: 0x03000020
- // ADC1: 0x03000040
- // DAC: 0x03000060
- // comparator: 0x03000080
- // RC osc: 0x030000a0
- // SPI slave: 0x030000c0 (read-only)
-
- // Memory map details:
- // GPIO: 32 channels total.
- // addr 0x03000000 data (16 bits)
- // addr 0x03000001 out (=1) or in (=0) (default 0)
- // addr 0x03000002 pu (=1) or none (=0) (default 0)
- // addr 0x03000003 pd (=1) or none (=0) (default 0)
- // addr 0x03000004-f reserved (may be used for other pad I/O)
- //
- // ADC0: addr 0x03000020 enable
- // addr 0x03000021 data (read-only)
- // addr 0x03000022 done (read-only)
- // addr 0x03000023 start conversion
- // addr 0x03000024 clock source (RC osc, SPI clk, xtal, core)
- // addr 0x03000025 input source (core VDD, ext, DAC, comp in)
- //
- // ADC1: addr 0x03000040 enable
- // addr 0x03000041 data (read-only)
- // addr 0x03000042 done (read-only)
- // addr 0x03000043 start conversion
- // addr 0x03000044 clock source (RC osc, SPI clk, xtal, core)
- // addr 0x03000045 input source (bg, ext, I/O vdd, gnd)
- //
- // DAC: addr 0x03000060 enable
- // addr 0x03000061 value
- //
- // comparator: addr 0x03000080 enable
- // addr 0x03000081 value
- // addr 0x03000082 input source (DAC, bg, core VDD, ext)
- // addr 0x03000083 output dest (ext gpio pin 0-1, IRQ, none)
- //
- // bandgap: addr 0x03000090 enable
- //
- // RC osc: addr 0x030000a0 enable
- // addr 0x030000a1 output dest (ext gpio pin 2-4)
- //
- // SPI slave: addr 0x030000c0 SPI configuration
- // addr 0x030000c1 xtal osc, reg, bg enables
- // addr 0x030000c2 PLL enables, trim
- // addr 0x030000c3 manufacturer ID
- // addr 0x030000c4 product ID
- // addr 0x030000c5 product mask revision
- // Xtal mon: addr 0x030000c6 xtal osc output dest (ext gpio pin 5-7)
- // PLL mon: addr 0x030000c7 PLL output dest (ext gpio pin 8-10)
- // trap mon: addr 0x030000c8 trap output dest (ext gpio pin 11-13)
- // IRQ7 src: addr 0x030000c9 IRQ 7 source (ext gpio pin 0-3)
- // IRQ8 src: addr 0x030000ca IRQ 8 source (ext gpio pin 4-7)
- // Analog: addr 0x030000cb analog output select (DAC, bg)
- //
- // Overtemp: addr 0x030000e0 over-temperature alarm enable
- // addr 0x030000e1 over-temperature alarm data
- // addr 0x030000e2 output dest (ext gpio pin 14-15, IRQ)
-
- always @(posedge clk) begin
- if (!resetn) begin
- gpio <= 0;
- gpio_oeb <= 16'hffff;
- gpio_pu <= 0;
- gpio_pd <= 0;
- adc0_ena <= 0;
- adc0_convert <= 0;
- adc0_clksrc <= 0;
- adc0_inputsrc <= 0;
- adc1_ena <= 0;
- adc1_convert <= 0;
- adc1_clksrc <= 0;
- adc1_inputsrc <= 0;
- dac_ena <= 0;
- dac_value <= 0;
- comp_ena <= 0;
- comp_ninputsrc <= 0;
- comp_pinputsrc <= 0;
- rcosc_ena <= 0;
- comp_output_dest <= 0;
- rcosc_output_dest <= 0;
- overtemp_dest <= 0;
- overtemp_ena <= 0;
- pll_output_dest <= 0;
- xtal_output_dest <= 0;
- trap_output_dest <= 0;
- irq_7_inputsrc <= 0;
- irq_8_inputsrc <= 0;
- analog_out_sel <= 0;
- opamp_ena <= 0;
- opamp_bias_ena <= 0;
- bg_ena <= 0;
-
- end else begin
- iomem_ready <= 0;
- if (iomem_valid && !iomem_ready && iomem_addr[31:8] == 24'h030000) begin
- iomem_ready <= 1;
- if (iomem_addr[7:0] == 8'h00) begin
- iomem_rdata <= {gpio_out, gpio_in};
- if (iomem_wstrb[0]) gpio[ 7: 0] <= iomem_wdata[ 7: 0];
- if (iomem_wstrb[1]) gpio[15: 8] <= iomem_wdata[15: 8];
- end else if (iomem_addr[7:0] == 8'h04) begin
- iomem_rdata <= {16'd0, gpio_oeb};
- if (iomem_wstrb[0]) gpio_oeb[ 7: 0] <= iomem_wdata[ 7: 0];
- if (iomem_wstrb[1]) gpio_oeb[15: 8] <= iomem_wdata[15: 8];
- end else if (iomem_addr[7:0] == 8'h08) begin
- iomem_rdata <= {16'd0, gpio_pu};
- if (iomem_wstrb[0]) gpio_pu[ 7: 0] <= iomem_wdata[ 7: 0];
- if (iomem_wstrb[1]) gpio_pu[15: 8] <= iomem_wdata[15: 8];
- end else if (iomem_addr[7:0] == 8'h0c) begin
- iomem_rdata <= {16'd0, gpio_pu};
- if (iomem_wstrb[0]) gpio_pd[ 7: 0] <= iomem_wdata[ 7: 0];
- if (iomem_wstrb[1]) gpio_pd[15: 8] <= iomem_wdata[15: 8];
- end else if (iomem_addr[7:0] == 8'h10) begin
- iomem_rdata <= {31'd0, adc0_ena};
- if (iomem_wstrb[0]) adc0_ena <= iomem_wdata[0];
- end else if (iomem_addr[7:0] == 8'h14) begin
- iomem_rdata <= {22'd0, adc0_data};
- end else if (iomem_addr[7:0] == 8'h18) begin
- iomem_rdata <= {31'd0, adc0_done};
- end else if (iomem_addr[7:0] == 8'h1c) begin
- iomem_rdata <= {31'd0, adc0_convert};
- if (iomem_wstrb[0]) adc0_convert <= iomem_wdata[0];
- end else if (iomem_addr[7:0] == 8'h20) begin
- iomem_rdata <= {30'd0, adc0_clksrc};
- if (iomem_wstrb[0]) adc0_clksrc <= iomem_wdata[1:0];
- end else if (iomem_addr[7:0] == 8'h24) begin
- iomem_rdata <= {30'd0, adc0_inputsrc};
- if (iomem_wstrb[0]) adc0_inputsrc <= iomem_wdata[1:0];
- end else if (iomem_addr[7:0] == 8'h30) begin
- iomem_rdata <= {31'd0, adc1_ena};
- if (iomem_wstrb[0]) adc1_ena <= iomem_wdata[0];
- end else if (iomem_addr[7:0] == 8'h34) begin
- iomem_rdata <= {22'd0, adc1_data};
- end else if (iomem_addr[7:0] == 8'h38) begin
- iomem_rdata <= {31'd0, adc1_done};
- end else if (iomem_addr[7:0] == 8'h3c) begin
- iomem_rdata <= {31'd0, adc1_convert};
- if (iomem_wstrb[0]) adc1_convert <= iomem_wdata[0];
- end else if (iomem_addr[7:0] == 8'h40) begin
- iomem_rdata <= {30'd0, adc1_clksrc};
- if (iomem_wstrb[0]) adc1_clksrc <= iomem_wdata[1:0];
- end else if (iomem_addr[7:0] == 8'h44) begin
- iomem_rdata <= {30'd0, adc1_inputsrc};
- if (iomem_wstrb[0]) adc1_inputsrc <= iomem_wdata[1:0];
- end else if (iomem_addr[7:0] == 8'h50) begin
- iomem_rdata <= {31'd0, dac_ena};
- if (iomem_wstrb[0]) dac_ena <= iomem_wdata[0];
- end else if (iomem_addr[7:0] == 8'h54) begin
- iomem_rdata <= {22'd0, dac_value};
- if (iomem_wstrb[0]) dac_value[7:0] <= iomem_wdata[7:0];
- if (iomem_wstrb[1]) dac_value[9:8] <= iomem_wdata[9:8];
- end else if (iomem_addr[7:0] == 8'h60) begin
- iomem_rdata <= {31'd0, comp_ena};
- if (iomem_wstrb[0]) comp_ena <= iomem_wdata[0];
- end else if (iomem_addr[7:0] == 8'h64) begin
- iomem_rdata <= {30'd0, comp_ninputsrc};
- if (iomem_wstrb[0]) comp_ninputsrc <= iomem_wdata[1:0];
- end else if (iomem_addr[7:0] == 8'h68) begin
- iomem_rdata <= {30'd0, comp_pinputsrc};
- if (iomem_wstrb[0]) comp_pinputsrc <= iomem_wdata[1:0];
- end else if (iomem_addr[7:0] == 8'h6c) begin
- iomem_rdata <= {30'd0, comp_output_dest};
- if (iomem_wstrb[0]) comp_output_dest <= iomem_wdata[1:0];
- end else if (iomem_addr[7:0] == 8'h70) begin
- iomem_rdata <= {31'd0, rcosc_ena};
- if (iomem_wstrb[0]) rcosc_ena <= iomem_wdata[0];
- end else if (iomem_addr[7:0] == 8'h74) begin
- iomem_rdata <= {30'd0, rcosc_output_dest};
- if (iomem_wstrb[0]) rcosc_output_dest <= iomem_wdata[1:0];
- end else if (iomem_addr[7:0] == 8'h80) begin
- iomem_rdata <= {24'd0, spi_ro_config};
- end else if (iomem_addr[7:0] == 8'h84) begin
- iomem_rdata <= {30'd0, spi_ro_xtal_ena, spi_ro_reg_ena};
- end else if (iomem_addr[7:0] == 8'h88) begin
- iomem_rdata <= {25'd0, spi_ro_pll_trim, spi_ro_pll_cp_ena, spi_ro_pll_vco_ena, spi_ro_pll_bias_ena};
- end else if (iomem_addr[7:0] == 8'h8c) begin
- iomem_rdata <= {20'd0, spi_ro_mfgr_id};
- end else if (iomem_addr[7:0] == 8'h90) begin
- iomem_rdata <= {24'd0, spi_ro_prod_id};
- end else if (iomem_addr[7:0] == 8'h94) begin
- iomem_rdata <= {28'd0, spi_ro_mask_rev};
- end else if (iomem_addr[7:0] == 8'h98) begin
- iomem_rdata <= {31'd0, ext_clk_sel};
- end else if (iomem_addr[7:0] == 8'ha0) begin
- iomem_rdata <= {30'd0, xtal_output_dest};
- if (iomem_wstrb[0]) xtal_output_dest <= iomem_wdata[1:0];
- end else if (iomem_addr[7:0] == 8'ha4) begin
- iomem_rdata <= {30'd0, pll_output_dest};
- if (iomem_wstrb[0]) pll_output_dest <= iomem_wdata[1:0];
- end else if (iomem_addr[7:0] == 8'ha8) begin
- iomem_rdata <= {30'd0, trap_output_dest};
- if (iomem_wstrb[0]) trap_output_dest <= iomem_wdata[1:0];
- end else if (iomem_addr[7:0] == 8'hb0) begin
- iomem_rdata <= {30'd0, irq_7_inputsrc};
- if (iomem_wstrb[0]) irq_7_inputsrc <= iomem_wdata[1:0];
- end else if (iomem_addr[7:0] == 8'hb4) begin
- iomem_rdata <= {30'd0, irq_8_inputsrc};
- if (iomem_wstrb[0]) irq_8_inputsrc <= iomem_wdata[1:0];
- end else if (iomem_addr[7:0] == 8'hc0) begin
- iomem_rdata <= {31'd0, analog_out_sel};
- if (iomem_wstrb[0]) analog_out_sel <= iomem_wdata[0];
- end else if (iomem_addr[7:0] == 8'hc4) begin
- iomem_rdata <= {31'd0, opamp_bias_ena};
- if (iomem_wstrb[0]) opamp_bias_ena <= iomem_wdata[0];
- end else if (iomem_addr[7:0] == 8'hc8) begin
- iomem_rdata <= {31'd0, opamp_ena};
- if (iomem_wstrb[0]) opamp_ena <= iomem_wdata[0];
- end else if (iomem_addr[7:0] == 8'hd0) begin
- iomem_rdata <= {31'd0, bg_ena};
- if (iomem_wstrb[0]) bg_ena <= iomem_wdata[0];
- end else if (iomem_addr[7:0] == 8'he0) begin
- iomem_rdata <= {31'd0, overtemp_ena};
- if (iomem_wstrb[0]) overtemp_ena <= iomem_wdata[0];
- end else if (iomem_addr[7:0] == 8'he4) begin
- iomem_rdata <= {31'd0, overtemp};
- end else if (iomem_addr[7:0] == 8'he8) begin
- iomem_rdata <= {30'd0, overtemp_dest};
- if (iomem_wstrb[0]) overtemp_dest <= iomem_wdata[1:0];
- end
- end
- end
- end
-
- openstriVe_soc_mem #(.WORDS(MEM_WORDS)) picomem (
- .clk(clk),
- .ena(resetn),
- .wen((mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS) ? mem_wstrb : 4'b0),
- .addr(mem_addr[23:2]),
- .wdata(mem_wdata),
- .rdata(ram_rdata)
- );
-endmodule
-
-`include "picorv32.v"
-`include "spimemio.v"
-`include "simpleuart.v"
-
-// Implementation note:
-// Replace the following two modules with wrappers for your SRAM cells.
-
-module openstriVe_soc_regs (
- input clk, wen,
- input [5:0] waddr,
- input [5:0] raddr1,
- input [5:0] raddr2,
- input [31:0] wdata,
- output [31:0] rdata1,
- output [31:0] rdata2
-);
- reg [31:0] regs [0:31];
-
- always @(posedge clk)
- if (wen) regs[waddr[4:0]] <= wdata;
-
- assign rdata1 = regs[raddr1[4:0]];
- assign rdata2 = regs[raddr2[4:0]];
-endmodule
-
-module openstriVe_soc_mem #(
- parameter integer WORDS = 256
-) (
- input clk,
- input ena,
- input [3:0] wen,
- input [21:0] addr,
- input [31:0] wdata,
- output reg [31:0] rdata
-);
- reg [31:0] mem [0:WORDS-1];
-
- always @(posedge clk) begin
- if (ena == 1'b1) begin
- rdata <= mem[addr];
- if (wen[0]) mem[addr][ 7: 0] <= wdata[ 7: 0];
- if (wen[1]) mem[addr][15: 8] <= wdata[15: 8];
- if (wen[2]) mem[addr][23:16] <= wdata[23:16];
- if (wen[3]) mem[addr][31:24] <= wdata[31:24];
- end
- end
-endmodule
-
diff --git a/designs/striVe_flat/src/digital_pll/cells.v b/designs/striVe_flat/src/digital_pll/cells.v
deleted file mode 100644
index b84aa50..0000000
--- a/designs/striVe_flat/src/digital_pll/cells.v
+++ /dev/null
@@ -1,32 +0,0 @@
-(* blackbox *)
-module efs8hd_dfrbp_2 (output QN, input D, input CLK, output Q, input RESETB); endmodule
-(* blackbox *)
-module efs8hd_inv_4 (input A, output Y); endmodule
-(* blackbox *)
-module efs8hd_buf_1(input A, output X); endmodule
-(* blackbox *)
-module efs8hd_clkbuf_1(input A, output X); endmodule
-(* blackbox *)
-module efs8hd_clkbuf_2(input A, output X); endmodule
-(* blackbox *)
-module efs8hd_clkinv_1(input A, output Y); endmodule
-(* blackbox *)
-module efs8hd_clkinv_2(input A, output Y); endmodule
-(* blackbox *)
-module efs8hd_clkinv_4(input A, output Y); endmodule
-(* blackbox *)
-module efs8hd_clkinv_8(input A, output Y); endmodule
-(* blackbox *)
-module efs8hd_conb_1(output HI, output LO); endmodule
-(* blackbox *)
-module efs8hd_dfbbp_1(input CLK, input D, output Q, output QN, input RESETB, input SETB); endmodule
-(* blackbox *)
-module efs8hd_einvn_4(input A, input TEB, output Z); endmodule
-(* blackbox *)
-module efs8hd_einvn_8(input A, input TEB, output Z); endmodule
-(* blackbox *)
-module efs8hd_einvp_1(input A, input TE, output Z); endmodule
-(* blackbox *)
-module efs8hd_einvp_2(input A, input TE, output Z); endmodule
-(* blackbox *)
-module efs8hd_or2_2(input A, B, output X); endmodule
diff --git a/designs/striVe_flat/src/digital_pll/digital_pll_controller.v b/designs/striVe_flat/src/digital_pll/digital_pll_controller.v
deleted file mode 100755
index b88cc33..0000000
--- a/designs/striVe_flat/src/digital_pll/digital_pll_controller.v
+++ /dev/null
@@ -1,115 +0,0 @@
-// (True) digital PLL
-//
-// Output goes to a trimmable ring oscillator (see documentation).
-// Ring oscillator should be trimmable to above and below maximum
-// ranges of the input.
-//
-// Input "osc" comes from a fixed clock source (e.g., crystal oscillator
-// output).
-//
-// Input "div" is the target number of clock cycles per oscillator cycle.
-// e.g., if div == 8 then this is an 8X PLL.
-//
-// Clock "clock" is the PLL output being trimmed.
-// (NOTE: To be done: Pass-through enable)
-//
-// Algorithm:
-//
-// 1) Trim is done by thermometer code. Reset to the highest value
-// in case the fastest rate clock is too fast for the logic.
-//
-// 2) Count the number of contiguous 1s and 0s in "osc"
-// periods of the master clock. If the count maxes out, it does
-// not roll over.
-//
-// 3) Add the two counts together.
-//
-// 4) If the sum is less than div, then the clock is too slow, so
-// decrease the trim code. If the sum is greater than div, the
-// clock is too fast, so increase the trim code. If the sum
-// is equal to div, the the trim code does not change.
-//
-
-module digital_pll_controller(reset, clock, osc, div, trim);
- input reset;
- input clock;
- input osc;
- input [4:0] div;
- output [25:0] trim; // Use ring_osc2x13, with 26 trim bits
-
- wire [25:0] trim;
- reg [2:0] oscbuf;
- reg [2:0] prep;
-
- reg [4:0] count0;
- reg [4:0] count1;
- reg [6:0] tval; // Includes 2 bits fractional
- wire [4:0] tint; // Integer part of the above
-
- wire [5:0] sum;
-
- assign sum = count0 + count1;
-
- // Integer to thermometer code (maybe there's an algorithmic way?)
- assign tint = tval[6:2];
- // |<--second-->|<-- first-->|
- assign trim = (tint == 5'd0) ? 26'b0000000000000_0000000000000 :
- (tint == 5'd1) ? 26'b0000000000000_0000000000001 :
- (tint == 5'd2) ? 26'b0000000000000_0000001000001 :
- (tint == 5'd3) ? 26'b0000000000000_0010001000001 :
- (tint == 5'd4) ? 26'b0000000000000_0010001001001 :
- (tint == 5'd5) ? 26'b0000000000000_0010101001001 :
- (tint == 5'd6) ? 26'b0000000000000_1010101001001 :
- (tint == 5'd7) ? 26'b0000000000000_1010101101001 :
- (tint == 5'd8) ? 26'b0000000000000_1010101101101 :
- (tint == 5'd9) ? 26'b0000000000000_1011101101101 :
- (tint == 5'd10) ? 26'b0000000000000_1011101111101 :
- (tint == 5'd11) ? 26'b0000000000000_1111101111101 :
- (tint == 5'd12) ? 26'b0000000000000_1111101111111 :
- (tint == 5'd13) ? 26'b0000000000000_1111111111111 :
- (tint == 5'd14) ? 26'b0000000000001_1111111111111 :
- (tint == 5'd15) ? 26'b0000001000001_1111111111111 :
- (tint == 5'd16) ? 26'b0010001000001_1111111111111 :
- (tint == 5'd17) ? 26'b0010001001001_1111111111111 :
- (tint == 5'd18) ? 26'b0010101001001_1111111111111 :
- (tint == 5'd19) ? 26'b1010101001001_1111111111111 :
- (tint == 5'd20) ? 26'b1010101101001_1111111111111 :
- (tint == 5'd21) ? 26'b1010101101101_1111111111111 :
- (tint == 5'd22) ? 26'b1011101101101_1111111111111 :
- (tint == 5'd23) ? 26'b1011101111101_1111111111111 :
- (tint == 5'd24) ? 26'b1111101111101_1111111111111 :
- (tint == 5'd25) ? 26'b1111101111111_1111111111111 :
- 26'b1111111111111_1111111111111;
-
- always @(posedge clock or posedge reset) begin
- if (reset == 1'b1) begin
- tval <= 7'd0; // Note: trim[0] must be zero for startup to work.
- oscbuf <= 3'd0;
- prep <= 3'd0;
- count0 <= 5'd0;
- count1 <= 5'd0;
-
- end else begin
- oscbuf <= {oscbuf[1:0], osc};
-
- if (oscbuf[2] != oscbuf[1]) begin
- count1 <= count0;
- count0 <= 5'b00001;
- prep <= {prep[1:0], 1'b1};
-
- if (prep == 3'b111) begin
- if (sum > div) begin
- tval <= tval + 1;
- end else if (sum < div) begin
- tval <= tval - 1;
- end
- end
- end else begin
- if (count0 != 5'b11111) begin
- count0 <= count0 + 1;
- end
- end
- end
- end
-
-endmodule // digital_pll_controller
diff --git a/designs/striVe_flat/src/digital_pll/ring_osc2x13.v b/designs/striVe_flat/src/digital_pll/ring_osc2x13.v
deleted file mode 100755
index eca5acf..0000000
--- a/designs/striVe_flat/src/digital_pll/ring_osc2x13.v
+++ /dev/null
@@ -1,179 +0,0 @@
-// Tunable ring oscillator---synthesizable (physical) version.
-//
-// NOTE: This netlist cannot be simulated correctly due to lack
-// of accurate timing in the digital cell verilog models.
-
-module delay_stage(in, trim, out);
- input in;
- input [1:0] trim;
- output out;
-
- wire d0, d1, d2;
-
- efs8hd_clkbuf_2 delaybuf0 (
- .A(in),
- .X(ts)
- );
-
- efs8hd_clkbuf_1 delaybuf1 (
- .A(ts),
- .X(d0)
- );
-
- efs8hd_einvp_2 delayen1 (
- .A(d0),
- .TE(trim[1]),
- .Z(d1)
- );
-
- efs8hd_einvn_4 delayenb1 (
- .A(ts),
- .TEB(trim[1]),
- .Z(d1)
- );
-
- efs8hd_clkinv_1 delayint0 (
- .A(d1),
- .Y(d2)
- );
-
- efs8hd_einvp_2 delayen0 (
- .A(d2),
- .TE(trim[0]),
- .Z(out)
- );
-
- efs8hd_einvn_8 delayenb0 (
- .A(ts),
- .TEB(trim[0]),
- .Z(out)
- );
-
-endmodule
-
-module start_stage(in, trim, reset, out);
- input in;
- input [1:0] trim;
- input reset;
- output out;
-
- wire d0, d1, d2, ctrl0, one;
-
- efs8hd_clkbuf_1 delaybuf0 (
- .A(in),
- .X(d0)
- );
-
- efs8hd_einvp_2 delayen1 (
- .A(d0),
- .TE(trim[1]),
- .Z(d1)
- );
-
- efs8hd_einvn_4 delayenb1 (
- .A(in),
- .TEB(trim[1]),
- .Z(d1)
- );
-
- efs8hd_clkinv_1 delayint0 (
- .A(d1),
- .Y(d2)
- );
-
- efs8hd_einvp_2 delayen0 (
- .A(d2),
- .TE(trim[0]),
- .Z(out)
- );
-
- efs8hd_einvn_8 delayenb0 (
- .A(in),
- .TEB(ctrl0),
- .Z(out)
- );
-
- efs8hd_einvp_1 reseten0 (
- .A(one),
- .TE(reset),
- .Z(out)
- );
-
- efs8hd_or2_2 ctrlen0 (
- .A(reset),
- .B(trim[0]),
- .X(ctrl0)
- );
-
- efs8hd_conb_1 const1 (
- .HI(one),
- .LO()
- );
-
-endmodule
-
-// Ring oscillator with 13 stages, each with two trim bits delay
-// (see above). Trim is not binary: For trim[1:0], lower bit
-// trim[0] is primary trim and must be applied first; upper
-// bit trim[1] is secondary trim and should only be applied
-// after the primary trim is applied, or it has no effect.
-//
-// Total effective number of inverter stages in this oscillator
-// ranges from 13 at trim 0 to 65 at trim 24. The intention is
-// to cover a range greater than 2x so that the midrange can be
-// reached over all PVT conditions.
-//
-// Frequency of this ring oscillator under SPICE simulations at
-// nominal PVT is maximum 214 MHz (trim 0), minimum 90 MHz (trim 24).
-
-module ring_osc2x13(reset, trim, clockp);
- input reset;
- input [25:0] trim;
- output[1:0] clockp;
-
- wire [12:0] d;
- wire [1:0] clockp;
- wire [1:0] c;
-
- // Main oscillator loop stages
-
- genvar i;
- generate
- for (i = 0; i < 12; i = i + 1) begin : dstage
- delay_stage id (
- .in(d[i]),
- .trim({trim[i+13], trim[i]}),
- .out(d[i+1])
- );
- end
- endgenerate
-
- // Reset/startup stage
-
- start_stage iss (
- .in(d[12]),
- .trim({trim[25], trim[12]}),
- .reset(reset),
- .out(d[0])
- );
-
- // Buffered outputs a 0 and 90 degrees phase (approximately)
-
- efs8hd_clkinv_2 ibufp00 (
- .A(d[0]),
- .Y(c[0])
- );
- efs8hd_clkinv_8 ibufp01 (
- .A(c[0]),
- .Y(clockp[0])
- );
- efs8hd_clkinv_2 ibufp10 (
- .A(d[6]),
- .Y(c[1])
- );
- efs8hd_clkinv_8 ibufp11 (
- .A(c[1]),
- .Y(clockp[1])
- );
-
-endmodule
diff --git a/designs/striVe_flat/src/openstriVe_soc/openstriVe_soc.v b/designs/striVe_flat/src/openstriVe_soc/striVe_soc.v
similarity index 81%
rename from designs/striVe_flat/src/openstriVe_soc/openstriVe_soc.v
rename to designs/striVe_flat/src/openstriVe_soc/striVe_soc.v
index 32e8eab..41dd8dc 100644
--- a/designs/striVe_flat/src/openstriVe_soc/openstriVe_soc.v
+++ b/designs/striVe_flat/src/openstriVe_soc/striVe_soc.v
@@ -57,11 +57,12 @@
*/
// Memory mapped I/O signals
- output [15:0] gpio_out, // Connect to out on gpio pad
- input [15:0] gpio_in, // Connect to in on gpio pad
- output [15:0] gpio_pullupb, // Connect to pullupb on gpio pad
- output [15:0] gpio_pulldownb, // Connect to pulldownb on gpio pad
- output [15:0] gpio_outenb, // Connect to outenb on gpio pad
+ output [15:0] gpio_out_pad, // Connect to out on gpio pad
+ input [15:0] gpio_in_pad, // Connect to in on gpio pad
+ output [15:0] gpio_mode0_pad, // Connect to dm[0] on gpio pad
+ output [15:0] gpio_mode1_pad, // Connect to dm[2] on gpio pad
+ output [15:0] gpio_outenb_pad, // Connect to oe_n on gpio pad
+ output [15:0] gpio_inenb_pad, // Connect to inp_dis on gpio pad
output adc0_ena,
output adc0_convert,
@@ -130,6 +131,14 @@
output flash_io2_oeb,
output flash_io3_oeb,
+ output flash_csb_ieb,
+ output flash_clk_ieb,
+
+ output flash_io0_ieb,
+ output flash_io1_ieb,
+ output flash_io2_ieb,
+ output flash_io3_ieb,
+
output flash_io0_do,
output flash_io1_do,
output flash_io2_do,
@@ -140,8 +149,9 @@
input flash_io2_di,
input flash_io3_di
);
- /* parameter integer MEM_WORDS = 256; */
/* Increase scratchpad memory to 1K words */
+ /* parameter integer MEM_WORDS = 1024; */
+ /* Memory reverted back to 256 words while memory has to be synthesized */
parameter integer MEM_WORDS = 256;
parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory
parameter [31:0] PROGADDR_RESET = 32'h 0010_0000; // 1 MB into flash
@@ -158,6 +168,11 @@
// memory-mapped I/O control registers
+ wire [15:0] gpio_pullup; // Intermediate GPIO pullup
+ wire [15:0] gpio_pulldown; // Intermediate GPIO pulldown
+ wire [15:0] gpio_outenb; // Intermediate GPIO out enable (bar)
+ wire [15:0] gpio_out; // Intermediate GPIO output
+
reg [15:0] gpio; // GPIO output data
reg [15:0] gpio_pu; // GPIO pull-up enable
reg [15:0] gpio_pd; // GPIO pull-down enable
@@ -217,7 +232,7 @@
assign resetn = ~(reset_delay[0] | ext_reset);
// ADC clock assignments
-
+
assign adc0_clk = (adc0_clksrc == 2'b00) ? rcosc_in :
(adc0_clksrc == 2'b01) ? spi_sck :
(adc0_clksrc == 2'b10) ? xtal_in :
@@ -235,9 +250,9 @@
assign gpio_out[2] = (rcosc_output_dest == 2'b01) ? rcosc_in : gpio[2];
assign gpio_out[3] = (rcosc_output_dest == 2'b10) ? rcosc_in : gpio[3];
assign gpio_out[4] = (rcosc_output_dest == 2'b11) ? rcosc_in : gpio[4];
- assign gpio_out[5] = (xtal_output_dest == 2'b01) ? xtal_in : gpio[5];
- assign gpio_out[6] = (xtal_output_dest == 2'b10) ? xtal_in : gpio[6];
- assign gpio_out[7] = (xtal_output_dest == 2'b11) ? xtal_in : gpio[7];
+ assign gpio_out[5] = (xtal_output_dest == 2'b01) ? xtal_in : gpio[5];
+ assign gpio_out[6] = (xtal_output_dest == 2'b10) ? xtal_in : gpio[6];
+ assign gpio_out[7] = (xtal_output_dest == 2'b11) ? xtal_in : gpio[7];
assign gpio_out[8] = (pll_output_dest == 2'b01) ? pll_clk : gpio[8];
assign gpio_out[9] = (pll_output_dest == 2'b10) ? pll_clk : gpio[9];
assign gpio_out[10] = (pll_output_dest == 2'b11) ? clk : gpio[10];
@@ -249,7 +264,7 @@
assign gpio_outenb[0] = (comp_output_dest == 2'b00) ? gpio_oeb[0] : 1'b0;
assign gpio_outenb[1] = (comp_output_dest == 2'b00) ? gpio_oeb[1] : 1'b0;
- assign gpio_outenb[2] = (rcosc_output_dest == 2'b00) ? gpio_oeb[2] : 1'b0;
+ assign gpio_outenb[2] = (rcosc_output_dest == 2'b00) ? gpio_oeb[2] : 1'b0;
assign gpio_outenb[3] = (rcosc_output_dest == 2'b00) ? gpio_oeb[3] : 1'b0;
assign gpio_outenb[4] = (rcosc_output_dest == 2'b00) ? gpio_oeb[4] : 1'b0;
assign gpio_outenb[5] = (xtal_output_dest == 2'b00) ? gpio_oeb[5] : 1'b0;
@@ -264,48 +279,61 @@
assign gpio_outenb[14] = (overtemp_dest == 2'b00) ? gpio_oeb[14] : 1'b0;
assign gpio_outenb[15] = (overtemp_dest == 2'b00) ? gpio_oeb[15] : 1'b0;
- assign gpio_pullupb[0] = (comp_output_dest == 2'b00) ? ~gpio_pu[0] : 1'b1;
- assign gpio_pullupb[1] = (comp_output_dest == 2'b00) ? ~gpio_pu[1] : 1'b1;
- assign gpio_pullupb[2] = (rcosc_output_dest == 2'b00) ? ~gpio_pu[2] : 1'b1;
- assign gpio_pullupb[3] = (rcosc_output_dest == 2'b00) ? ~gpio_pu[3] : 1'b1;
- assign gpio_pullupb[4] = (rcosc_output_dest == 2'b00) ? ~gpio_pu[4] : 1'b1;
- assign gpio_pullupb[5] = (xtal_output_dest == 2'b00) ? ~gpio_pu[5] : 1'b1;
- assign gpio_pullupb[6] = (xtal_output_dest == 2'b00) ? ~gpio_pu[6] : 1'b1;
- assign gpio_pullupb[7] = (xtal_output_dest == 2'b00) ? ~gpio_pu[7] : 1'b1;
- assign gpio_pullupb[8] = (pll_output_dest == 2'b00) ? ~gpio_pu[8] : 1'b1;
- assign gpio_pullupb[9] = (pll_output_dest == 2'b00) ? ~gpio_pu[9] : 1'b1;
- assign gpio_pullupb[10] = (pll_output_dest == 2'b00) ? ~gpio_pu[10] : 1'b1;
- assign gpio_pullupb[11] = (trap_output_dest == 2'b00) ? ~gpio_pu[11] : 1'b1;
- assign gpio_pullupb[12] = (trap_output_dest == 2'b00) ? ~gpio_pu[12] : 1'b1;
- assign gpio_pullupb[13] = (trap_output_dest == 2'b00) ? ~gpio_pu[13] : 1'b1;
- assign gpio_pullupb[14] = (overtemp_dest == 2'b00) ? ~gpio_pu[14] : 1'b1;
- assign gpio_pullupb[15] = (overtemp_dest == 2'b00) ? ~gpio_pu[15] : 1'b1;
+ assign gpio_pullup[0] = (comp_output_dest == 2'b00) ? gpio_pu[0] : 1'b0;
+ assign gpio_pullup[1] = (comp_output_dest == 2'b00) ? gpio_pu[1] : 1'b0;
+ assign gpio_pullup[2] = (rcosc_output_dest == 2'b00) ? gpio_pu[2] : 1'b0;
+ assign gpio_pullup[3] = (rcosc_output_dest == 2'b00) ? gpio_pu[3] : 1'b0;
+ assign gpio_pullup[4] = (rcosc_output_dest == 2'b00) ? gpio_pu[4] : 1'b0;
+ assign gpio_pullup[5] = (xtal_output_dest == 2'b00) ? gpio_pu[5] : 1'b0;
+ assign gpio_pullup[6] = (xtal_output_dest == 2'b00) ? gpio_pu[6] : 1'b0;
+ assign gpio_pullup[7] = (xtal_output_dest == 2'b00) ? gpio_pu[7] : 1'b0;
+ assign gpio_pullup[8] = (pll_output_dest == 2'b00) ? gpio_pu[8] : 1'b0;
+ assign gpio_pullup[9] = (pll_output_dest == 2'b00) ? gpio_pu[9] : 1'b0;
+ assign gpio_pullup[10] = (pll_output_dest == 2'b00) ? gpio_pu[10] : 1'b0;
+ assign gpio_pullup[11] = (trap_output_dest == 2'b00) ? gpio_pu[11] : 1'b0;
+ assign gpio_pullup[12] = (trap_output_dest == 2'b00) ? gpio_pu[12] : 1'b0;
+ assign gpio_pullup[13] = (trap_output_dest == 2'b00) ? gpio_pu[13] : 1'b0;
+ assign gpio_pullup[14] = (overtemp_dest == 2'b00) ? gpio_pu[14] : 1'b0;
+ assign gpio_pullup[15] = (overtemp_dest == 2'b00) ? gpio_pu[15] : 1'b0;
- assign gpio_pulldownb[0] = (comp_output_dest == 2'b00) ? ~gpio_pd[0] : 1'b1;
- assign gpio_pulldownb[1] = (comp_output_dest == 2'b00) ? ~gpio_pd[1] : 1'b1;
- assign gpio_pulldownb[2] = (rcosc_output_dest == 2'b00) ? ~gpio_pd[2] : 1'b1;
- assign gpio_pulldownb[3] = (rcosc_output_dest == 2'b00) ? ~gpio_pd[3] : 1'b1;
- assign gpio_pulldownb[4] = (rcosc_output_dest == 2'b00) ? ~gpio_pd[4] : 1'b1;
- assign gpio_pulldownb[5] = (xtal_output_dest == 2'b00) ? ~gpio_pd[5] : 1'b1;
- assign gpio_pulldownb[6] = (xtal_output_dest == 2'b00) ? ~gpio_pd[6] : 1'b1;
- assign gpio_pulldownb[7] = (xtal_output_dest == 2'b00) ? ~gpio_pd[7] : 1'b1;
- assign gpio_pulldownb[8] = (pll_output_dest == 2'b00) ? ~gpio_pd[8] : 1'b1;
- assign gpio_pulldownb[9] = (pll_output_dest == 2'b00) ? ~gpio_pd[9] : 1'b1;
- assign gpio_pulldownb[10] = (pll_output_dest == 2'b00) ? ~gpio_pd[10] : 1'b1;
- assign gpio_pulldownb[11] = (trap_output_dest == 2'b00) ? ~gpio_pd[11] : 1'b1;
- assign gpio_pulldownb[12] = (trap_output_dest == 2'b00) ? ~gpio_pd[12] : 1'b1;
- assign gpio_pulldownb[13] = (trap_output_dest == 2'b00) ? ~gpio_pd[13] : 1'b1;
- assign gpio_pulldownb[14] = (overtemp_dest == 2'b00) ? ~gpio_pd[14] : 1'b1;
- assign gpio_pulldownb[15] = (overtemp_dest == 2'b00) ? ~gpio_pd[15] : 1'b1;
+ assign gpio_pulldown[0] = (comp_output_dest == 2'b00) ? gpio_pd[0] : 1'b0;
+ assign gpio_pulldown[1] = (comp_output_dest == 2'b00) ? gpio_pd[1] : 1'b0;
+ assign gpio_pulldown[2] = (rcosc_output_dest == 2'b00) ? gpio_pd[2] : 1'b0;
+ assign gpio_pulldown[3] = (rcosc_output_dest == 2'b00) ? gpio_pd[3] : 1'b0;
+ assign gpio_pulldown[4] = (rcosc_output_dest == 2'b00) ? gpio_pd[4] : 1'b0;
+ assign gpio_pulldown[5] = (xtal_output_dest == 2'b00) ? gpio_pd[5] : 1'b0;
+ assign gpio_pulldown[6] = (xtal_output_dest == 2'b00) ? gpio_pd[6] : 1'b0;
+ assign gpio_pulldown[7] = (xtal_output_dest == 2'b00) ? gpio_pd[7] : 1'b0;
+ assign gpio_pulldown[8] = (pll_output_dest == 2'b00) ? gpio_pd[8] : 1'b0;
+ assign gpio_pulldown[9] = (pll_output_dest == 2'b00) ? gpio_pd[9] : 1'b0;
+ assign gpio_pulldown[10] = (pll_output_dest == 2'b00) ? gpio_pd[10] : 1'b0;
+ assign gpio_pulldown[11] = (trap_output_dest == 2'b00) ? gpio_pd[11] : 1'b0;
+ assign gpio_pulldown[12] = (trap_output_dest == 2'b00) ? gpio_pd[12] : 1'b0;
+ assign gpio_pulldown[13] = (trap_output_dest == 2'b00) ? gpio_pd[13] : 1'b0;
+ assign gpio_pulldown[14] = (overtemp_dest == 2'b00) ? gpio_pd[14] : 1'b0;
+ assign gpio_pulldown[15] = (overtemp_dest == 2'b00) ? gpio_pd[15] : 1'b0;
+
+ // Convert GPIO signals to s8 pad signals
+ convert_gpio_sigs convert_gpio_bit [15:0] (
+ .gpio_out(gpio_out),
+ .gpio_outenb(gpio_outenb),
+ .gpio_pu(gpio_pullup),
+ .gpio_pd(gpio_pulldown),
+ .gpio_out_pad(gpio_out_pad),
+ .gpio_outenb_pad(gpio_outenb_pad),
+ .gpio_inenb_pad(gpio_inenb_pad),
+ .gpio_mode1_pad(gpio_mode1_pad),
+ .gpio_mode0_pad(gpio_mode0_pad)
+ );
wire irq_7, irq_8;
- assign irq_7 = (irq_7_inputsrc == 2'b01) ? gpio_in[0] :
- (irq_7_inputsrc == 2'b10) ? gpio_in[1] :
- (irq_7_inputsrc == 2'b11) ? gpio_in[2] : 1'b0;
- assign irq_8 = (irq_8_inputsrc == 2'b01) ? gpio_in[3] :
- (irq_8_inputsrc == 2'b10) ? gpio_in[4] :
- (irq_8_inputsrc == 2'b11) ? gpio_in[5] : 1'b0;
+ assign irq_7 = (irq_7_inputsrc == 2'b01) ? gpio_in_pad[0] :
+ (irq_7_inputsrc == 2'b10) ? gpio_in_pad[1] :
+ (irq_7_inputsrc == 2'b11) ? gpio_in_pad[2] : 1'b0;
+ assign irq_8 = (irq_8_inputsrc == 2'b01) ? gpio_in_pad[3] :
+ (irq_8_inputsrc == 2'b10) ? gpio_in_pad[4] :
+ (irq_8_inputsrc == 2'b11) ? gpio_in_pad[5] : 1'b0;
assign ram_wenb = (mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS) ?
{~mem_wstrb[3], ~mem_wstrb[2], ~mem_wstrb[1], ~mem_wstrb[0]} : 4'b1111;
@@ -407,6 +435,14 @@
.flash_io2_oeb (flash_io2_oeb),
.flash_io3_oeb (flash_io3_oeb),
+ .flash_csb_ieb (flash_csb_oeb),
+ .flash_clk_ieb (flash_clk_oeb),
+
+ .flash_io0_ieb (flash_io0_ieb),
+ .flash_io1_ieb (flash_io1_ieb),
+ .flash_io2_ieb (flash_io2_ieb),
+ .flash_io3_ieb (flash_io3_ieb),
+
.flash_io0_do (flash_io0_do),
.flash_io1_do (flash_io1_do),
.flash_io2_do (flash_io2_do),
@@ -454,7 +490,7 @@
// 1 bandgap
// 1 power-on-reset (POR)
// 1 temperature alarm
-
+
// NOTE: Signals affecting critical core functions are controlled through
// an independent SPI having read-only access through the picorv32 core.
// SPI pins are independent of picorv32 SPI master. Signals controlled by
@@ -486,7 +522,7 @@
// SPI slave: 0x030000c0 (read-only)
// Memory map details:
- // GPIO: 32 channels total.
+ // GPIO: 32 channels total.
// addr 0x03000000 data (16 bits)
// addr 0x03000001 out (=1) or in (=0) (default 0)
// addr 0x03000002 pu (=1) or none (=0) (default 0)
@@ -576,7 +612,7 @@
if (iomem_valid && !iomem_ready && iomem_addr[31:8] == 24'h030000) begin
iomem_ready <= 1;
if (iomem_addr[7:0] == 8'h00) begin
- iomem_rdata <= {gpio_out, gpio_in};
+ iomem_rdata <= {gpio_out, gpio_in_pad};
if (iomem_wstrb[0]) gpio[ 7: 0] <= iomem_wdata[ 7: 0];
if (iomem_wstrb[1]) gpio[15: 8] <= iomem_wdata[15: 8];
end else if (iomem_addr[7:0] == 8'h04) begin
@@ -757,3 +793,36 @@
end
endmodule
+/* Convert the standard set of GPIO signals: input, output, output_enb,
+ * pullup, and pulldown into the set needed by the s8 GPIO pads:
+ * input, output, output_enb, input_enb, mode. Note that dm[2] on
+ * thepads is always equal to dm[1] in this setup, so mode is shown as
+ * only a 2-bit signal.
+ *
+ * This module is bit-sliced. Instantiate once for each GPIO pad.
+ */
+
+module convert_gpio_sigs (
+ input gpio_out,
+ input gpio_outenb,
+ input gpio_pu,
+ input gpio_pd,
+ output gpio_out_pad,
+ output gpio_outenb_pad,
+ output gpio_inenb_pad,
+ output gpio_mode1_pad,
+ output gpio_mode0_pad
+);
+
+ assign gpio_out_pad = (gpio_pu == 1'b0 && gpio_pd == 1'b0) ? gpio_out :
+ (gpio_pu == 1'b1) ? 1 : 0;
+
+ assign gpio_outenb_pad = (gpio_outenb == 1'b0) ? 0 :
+ (gpio_pu == 1'b1 || gpio_pd == 1'b1) ? 0 : 1;
+
+ assign gpio_inenb_pad = ~gpio_outenb;
+
+ assign gpio_mode1_pad = ~gpio_outenb_pad;
+ assign gpio_mode0_pad = ~gpio_outenb;
+
+endmodule
diff --git a/designs/striVe_flat/src/striVe_spi/cells.v b/designs/striVe_flat/src/striVe_spi/cells.v
deleted file mode 100644
index c0d3ca6..0000000
--- a/designs/striVe_flat/src/striVe_spi/cells.v
+++ /dev/null
@@ -1,4 +0,0 @@
-(* blackbox *)
-module scs8hvl_lsbufhv2lv_1(input A, output X); endmodule
-(* blackbox *)
-module scs8hvl_lsbuflv2hv_1(input A, output X); endmodule
diff --git a/designs/openstriVe_soc/config.tcl b/designs/striVe_soc/config.tcl
similarity index 78%
rename from designs/openstriVe_soc/config.tcl
rename to designs/striVe_soc/config.tcl
index 44b47e8..660f280 100644
--- a/designs/openstriVe_soc/config.tcl
+++ b/designs/striVe_soc/config.tcl
@@ -1,6 +1,6 @@
-set ::env(DESIGN_NAME) "openstriVe_soc"
+set ::env(DESIGN_NAME) "striVe_soc"
-set ::env(VERILOG_FILES) "./designs/openstriVe_soc/src/openstriVe_soc.v"
+set ::env(VERILOG_FILES) "./designs/striVe_soc/src/striVe_soc.v"
set ::env(CLOCK_PERIOD) "10"
# which clock port ??
diff --git a/designs/openstriVe_soc/src/picorv32.v b/designs/striVe_soc/src/picorv32.v
similarity index 100%
rename from designs/openstriVe_soc/src/picorv32.v
rename to designs/striVe_soc/src/picorv32.v
diff --git a/designs/openstriVe_soc/src/simpleuart.v b/designs/striVe_soc/src/simpleuart.v
similarity index 100%
rename from designs/openstriVe_soc/src/simpleuart.v
rename to designs/striVe_soc/src/simpleuart.v
diff --git a/designs/openstriVe_soc/src/spimemio.v b/designs/striVe_soc/src/spimemio.v
similarity index 100%
rename from designs/openstriVe_soc/src/spimemio.v
rename to designs/striVe_soc/src/spimemio.v
diff --git a/designs/striVe_flat/src/openstriVe_soc/openstriVe_soc.v b/designs/striVe_soc/src/striVe_soc.v
similarity index 81%
copy from designs/striVe_flat/src/openstriVe_soc/openstriVe_soc.v
copy to designs/striVe_soc/src/striVe_soc.v
index 32e8eab..9fe97d8 100644
--- a/designs/striVe_flat/src/openstriVe_soc/openstriVe_soc.v
+++ b/designs/striVe_soc/src/striVe_soc.v
@@ -24,6 +24,7 @@
*/
`ifdef PICORV32_V
+`error "openstriVe_soc.v must be read before picorv32.v!"
`endif
/* Note: Synthesize register memory from flops */
@@ -36,7 +37,7 @@
`define PICORV32_REGS openstriVe_soc_regs
-module openstriVe_soc (
+module striVe_soc (
`ifdef LVS
inout vdd1v8, /* 1.8V domain */
inout vss,
@@ -57,11 +58,12 @@
*/
// Memory mapped I/O signals
- output [15:0] gpio_out, // Connect to out on gpio pad
- input [15:0] gpio_in, // Connect to in on gpio pad
- output [15:0] gpio_pullupb, // Connect to pullupb on gpio pad
- output [15:0] gpio_pulldownb, // Connect to pulldownb on gpio pad
- output [15:0] gpio_outenb, // Connect to outenb on gpio pad
+ output [15:0] gpio_out_pad, // Connect to out on gpio pad
+ input [15:0] gpio_in_pad, // Connect to in on gpio pad
+ output [15:0] gpio_mode0_pad, // Connect to dm[0] on gpio pad
+ output [15:0] gpio_mode1_pad, // Connect to dm[2] on gpio pad
+ output [15:0] gpio_outenb_pad, // Connect to oe_n on gpio pad
+ output [15:0] gpio_inenb_pad, // Connect to inp_dis on gpio pad
output adc0_ena,
output adc0_convert,
@@ -130,6 +132,14 @@
output flash_io2_oeb,
output flash_io3_oeb,
+ output flash_csb_ieb,
+ output flash_clk_ieb,
+
+ output flash_io0_ieb,
+ output flash_io1_ieb,
+ output flash_io2_ieb,
+ output flash_io3_ieb,
+
output flash_io0_do,
output flash_io1_do,
output flash_io2_do,
@@ -140,8 +150,9 @@
input flash_io2_di,
input flash_io3_di
);
- /* parameter integer MEM_WORDS = 256; */
/* Increase scratchpad memory to 1K words */
+ /* parameter integer MEM_WORDS = 1024; */
+ /* Memory reverted back to 256 words while memory has to be synthesized */
parameter integer MEM_WORDS = 256;
parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory
parameter [31:0] PROGADDR_RESET = 32'h 0010_0000; // 1 MB into flash
@@ -158,6 +169,11 @@
// memory-mapped I/O control registers
+ wire [15:0] gpio_pullup; // Intermediate GPIO pullup
+ wire [15:0] gpio_pulldown; // Intermediate GPIO pulldown
+ wire [15:0] gpio_outenb; // Intermediate GPIO out enable (bar)
+ wire [15:0] gpio_out; // Intermediate GPIO output
+
reg [15:0] gpio; // GPIO output data
reg [15:0] gpio_pu; // GPIO pull-up enable
reg [15:0] gpio_pd; // GPIO pull-down enable
@@ -264,48 +280,61 @@
assign gpio_outenb[14] = (overtemp_dest == 2'b00) ? gpio_oeb[14] : 1'b0;
assign gpio_outenb[15] = (overtemp_dest == 2'b00) ? gpio_oeb[15] : 1'b0;
- assign gpio_pullupb[0] = (comp_output_dest == 2'b00) ? ~gpio_pu[0] : 1'b1;
- assign gpio_pullupb[1] = (comp_output_dest == 2'b00) ? ~gpio_pu[1] : 1'b1;
- assign gpio_pullupb[2] = (rcosc_output_dest == 2'b00) ? ~gpio_pu[2] : 1'b1;
- assign gpio_pullupb[3] = (rcosc_output_dest == 2'b00) ? ~gpio_pu[3] : 1'b1;
- assign gpio_pullupb[4] = (rcosc_output_dest == 2'b00) ? ~gpio_pu[4] : 1'b1;
- assign gpio_pullupb[5] = (xtal_output_dest == 2'b00) ? ~gpio_pu[5] : 1'b1;
- assign gpio_pullupb[6] = (xtal_output_dest == 2'b00) ? ~gpio_pu[6] : 1'b1;
- assign gpio_pullupb[7] = (xtal_output_dest == 2'b00) ? ~gpio_pu[7] : 1'b1;
- assign gpio_pullupb[8] = (pll_output_dest == 2'b00) ? ~gpio_pu[8] : 1'b1;
- assign gpio_pullupb[9] = (pll_output_dest == 2'b00) ? ~gpio_pu[9] : 1'b1;
- assign gpio_pullupb[10] = (pll_output_dest == 2'b00) ? ~gpio_pu[10] : 1'b1;
- assign gpio_pullupb[11] = (trap_output_dest == 2'b00) ? ~gpio_pu[11] : 1'b1;
- assign gpio_pullupb[12] = (trap_output_dest == 2'b00) ? ~gpio_pu[12] : 1'b1;
- assign gpio_pullupb[13] = (trap_output_dest == 2'b00) ? ~gpio_pu[13] : 1'b1;
- assign gpio_pullupb[14] = (overtemp_dest == 2'b00) ? ~gpio_pu[14] : 1'b1;
- assign gpio_pullupb[15] = (overtemp_dest == 2'b00) ? ~gpio_pu[15] : 1'b1;
+ assign gpio_pullup[0] = (comp_output_dest == 2'b00) ? gpio_pu[0] : 1'b0;
+ assign gpio_pullup[1] = (comp_output_dest == 2'b00) ? gpio_pu[1] : 1'b0;
+ assign gpio_pullup[2] = (rcosc_output_dest == 2'b00) ? gpio_pu[2] : 1'b0;
+ assign gpio_pullup[3] = (rcosc_output_dest == 2'b00) ? gpio_pu[3] : 1'b0;
+ assign gpio_pullup[4] = (rcosc_output_dest == 2'b00) ? gpio_pu[4] : 1'b0;
+ assign gpio_pullup[5] = (xtal_output_dest == 2'b00) ? gpio_pu[5] : 1'b0;
+ assign gpio_pullup[6] = (xtal_output_dest == 2'b00) ? gpio_pu[6] : 1'b0;
+ assign gpio_pullup[7] = (xtal_output_dest == 2'b00) ? gpio_pu[7] : 1'b0;
+ assign gpio_pullup[8] = (pll_output_dest == 2'b00) ? gpio_pu[8] : 1'b0;
+ assign gpio_pullup[9] = (pll_output_dest == 2'b00) ? gpio_pu[9] : 1'b0;
+ assign gpio_pullup[10] = (pll_output_dest == 2'b00) ? gpio_pu[10] : 1'b0;
+ assign gpio_pullup[11] = (trap_output_dest == 2'b00) ? gpio_pu[11] : 1'b0;
+ assign gpio_pullup[12] = (trap_output_dest == 2'b00) ? gpio_pu[12] : 1'b0;
+ assign gpio_pullup[13] = (trap_output_dest == 2'b00) ? gpio_pu[13] : 1'b0;
+ assign gpio_pullup[14] = (overtemp_dest == 2'b00) ? gpio_pu[14] : 1'b0;
+ assign gpio_pullup[15] = (overtemp_dest == 2'b00) ? gpio_pu[15] : 1'b0;
- assign gpio_pulldownb[0] = (comp_output_dest == 2'b00) ? ~gpio_pd[0] : 1'b1;
- assign gpio_pulldownb[1] = (comp_output_dest == 2'b00) ? ~gpio_pd[1] : 1'b1;
- assign gpio_pulldownb[2] = (rcosc_output_dest == 2'b00) ? ~gpio_pd[2] : 1'b1;
- assign gpio_pulldownb[3] = (rcosc_output_dest == 2'b00) ? ~gpio_pd[3] : 1'b1;
- assign gpio_pulldownb[4] = (rcosc_output_dest == 2'b00) ? ~gpio_pd[4] : 1'b1;
- assign gpio_pulldownb[5] = (xtal_output_dest == 2'b00) ? ~gpio_pd[5] : 1'b1;
- assign gpio_pulldownb[6] = (xtal_output_dest == 2'b00) ? ~gpio_pd[6] : 1'b1;
- assign gpio_pulldownb[7] = (xtal_output_dest == 2'b00) ? ~gpio_pd[7] : 1'b1;
- assign gpio_pulldownb[8] = (pll_output_dest == 2'b00) ? ~gpio_pd[8] : 1'b1;
- assign gpio_pulldownb[9] = (pll_output_dest == 2'b00) ? ~gpio_pd[9] : 1'b1;
- assign gpio_pulldownb[10] = (pll_output_dest == 2'b00) ? ~gpio_pd[10] : 1'b1;
- assign gpio_pulldownb[11] = (trap_output_dest == 2'b00) ? ~gpio_pd[11] : 1'b1;
- assign gpio_pulldownb[12] = (trap_output_dest == 2'b00) ? ~gpio_pd[12] : 1'b1;
- assign gpio_pulldownb[13] = (trap_output_dest == 2'b00) ? ~gpio_pd[13] : 1'b1;
- assign gpio_pulldownb[14] = (overtemp_dest == 2'b00) ? ~gpio_pd[14] : 1'b1;
- assign gpio_pulldownb[15] = (overtemp_dest == 2'b00) ? ~gpio_pd[15] : 1'b1;
+ assign gpio_pulldown[0] = (comp_output_dest == 2'b00) ? gpio_pd[0] : 1'b0;
+ assign gpio_pulldown[1] = (comp_output_dest == 2'b00) ? gpio_pd[1] : 1'b0;
+ assign gpio_pulldown[2] = (rcosc_output_dest == 2'b00) ? gpio_pd[2] : 1'b0;
+ assign gpio_pulldown[3] = (rcosc_output_dest == 2'b00) ? gpio_pd[3] : 1'b0;
+ assign gpio_pulldown[4] = (rcosc_output_dest == 2'b00) ? gpio_pd[4] : 1'b0;
+ assign gpio_pulldown[5] = (xtal_output_dest == 2'b00) ? gpio_pd[5] : 1'b0;
+ assign gpio_pulldown[6] = (xtal_output_dest == 2'b00) ? gpio_pd[6] : 1'b0;
+ assign gpio_pulldown[7] = (xtal_output_dest == 2'b00) ? gpio_pd[7] : 1'b0;
+ assign gpio_pulldown[8] = (pll_output_dest == 2'b00) ? gpio_pd[8] : 1'b0;
+ assign gpio_pulldown[9] = (pll_output_dest == 2'b00) ? gpio_pd[9] : 1'b0;
+ assign gpio_pulldown[10] = (pll_output_dest == 2'b00) ? gpio_pd[10] : 1'b0;
+ assign gpio_pulldown[11] = (trap_output_dest == 2'b00) ? gpio_pd[11] : 1'b0;
+ assign gpio_pulldown[12] = (trap_output_dest == 2'b00) ? gpio_pd[12] : 1'b0;
+ assign gpio_pulldown[13] = (trap_output_dest == 2'b00) ? gpio_pd[13] : 1'b0;
+ assign gpio_pulldown[14] = (overtemp_dest == 2'b00) ? gpio_pd[14] : 1'b0;
+ assign gpio_pulldown[15] = (overtemp_dest == 2'b00) ? gpio_pd[15] : 1'b0;
+
+ // Convert GPIO signals to s8 pad signals
+ convert_gpio_sigs convert_gpio_bit [15:0] (
+ .gpio_out(gpio_out),
+ .gpio_outenb(gpio_outenb),
+ .gpio_pu(gpio_pullup),
+ .gpio_pd(gpio_pulldown),
+ .gpio_out_pad(gpio_out_pad),
+ .gpio_outenb_pad(gpio_outenb_pad),
+ .gpio_inenb_pad(gpio_inenb_pad),
+ .gpio_mode1_pad(gpio_mode1_pad),
+ .gpio_mode0_pad(gpio_mode0_pad)
+ );
wire irq_7, irq_8;
- assign irq_7 = (irq_7_inputsrc == 2'b01) ? gpio_in[0] :
- (irq_7_inputsrc == 2'b10) ? gpio_in[1] :
- (irq_7_inputsrc == 2'b11) ? gpio_in[2] : 1'b0;
- assign irq_8 = (irq_8_inputsrc == 2'b01) ? gpio_in[3] :
- (irq_8_inputsrc == 2'b10) ? gpio_in[4] :
- (irq_8_inputsrc == 2'b11) ? gpio_in[5] : 1'b0;
+ assign irq_7 = (irq_7_inputsrc == 2'b01) ? gpio_in_pad[0] :
+ (irq_7_inputsrc == 2'b10) ? gpio_in_pad[1] :
+ (irq_7_inputsrc == 2'b11) ? gpio_in_pad[2] : 1'b0;
+ assign irq_8 = (irq_8_inputsrc == 2'b01) ? gpio_in_pad[3] :
+ (irq_8_inputsrc == 2'b10) ? gpio_in_pad[4] :
+ (irq_8_inputsrc == 2'b11) ? gpio_in_pad[5] : 1'b0;
assign ram_wenb = (mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS) ?
{~mem_wstrb[3], ~mem_wstrb[2], ~mem_wstrb[1], ~mem_wstrb[0]} : 4'b1111;
@@ -407,6 +436,14 @@
.flash_io2_oeb (flash_io2_oeb),
.flash_io3_oeb (flash_io3_oeb),
+ .flash_csb_ieb (flash_csb_ieb),
+ .flash_clk_ieb (flash_clk_ieb),
+
+ .flash_io0_ieb (flash_io0_ieb),
+ .flash_io1_ieb (flash_io1_ieb),
+ .flash_io2_ieb (flash_io2_ieb),
+ .flash_io3_ieb (flash_io3_ieb),
+
.flash_io0_do (flash_io0_do),
.flash_io1_do (flash_io1_do),
.flash_io2_do (flash_io2_do),
@@ -576,7 +613,7 @@
if (iomem_valid && !iomem_ready && iomem_addr[31:8] == 24'h030000) begin
iomem_ready <= 1;
if (iomem_addr[7:0] == 8'h00) begin
- iomem_rdata <= {gpio_out, gpio_in};
+ iomem_rdata <= {gpio_out, gpio_in_pad};
if (iomem_wstrb[0]) gpio[ 7: 0] <= iomem_wdata[ 7: 0];
if (iomem_wstrb[1]) gpio[15: 8] <= iomem_wdata[15: 8];
end else if (iomem_addr[7:0] == 8'h04) begin
@@ -712,6 +749,9 @@
);
endmodule
+`include "picorv32.v"
+`include "spimemio.v"
+`include "simpleuart.v"
// Implementation note:
// Replace the following two modules with wrappers for your SRAM cells.
@@ -757,3 +797,37 @@
end
endmodule
+/* Convert the standard set of GPIO signals: input, output, output_enb,
+ * pullup, and pulldown into the set needed by the s8 GPIO pads:
+ * input, output, output_enb, input_enb, mode. Note that dm[2] on
+ * thepads is always equal to dm[1] in this setup, so mode is shown as
+ * only a 2-bit signal.
+ *
+ * This module is bit-sliced. Instantiate once for each GPIO pad.
+ */
+
+module convert_gpio_sigs (
+ input gpio_out,
+ input gpio_outenb,
+ input gpio_pu,
+ input gpio_pd,
+ output gpio_out_pad,
+ output gpio_outenb_pad,
+ output gpio_inenb_pad,
+ output gpio_mode1_pad,
+ output gpio_mode0_pad
+);
+
+ assign gpio_out_pad = (gpio_pu == 1'b0 && gpio_pd == 1'b0) ? gpio_out :
+ (gpio_pu == 1'b1) ? 1 : 0;
+
+ assign gpio_outenb_pad = (gpio_outenb == 1'b0) ? 0 :
+ (gpio_pu == 1'b1 || gpio_pd == 1'b1) ? 0 : 1;
+
+ assign gpio_inenb_pad = ~gpio_outenb;
+
+ assign gpio_mode1_pad = ~gpio_outenb_pad;
+ assign gpio_mode0_pad = ~gpio_outenb;
+
+endmodule
+
diff --git a/pdks/ef-skywater-s8 b/pdks/ef-skywater-s8
index a5c75cd..dd3855f 160000
--- a/pdks/ef-skywater-s8
+++ b/pdks/ef-skywater-s8
@@ -1 +1 @@
-Subproject commit a5c75cd19720acfdbb2b50e1fc115c27ac01ec3f
+Subproject commit dd3855ffdb9023efe04ab0f9f4877e5a5e0f17d8
diff --git a/scripts/libtrim.pl b/scripts/libtrim.pl
index ce40891..0c5a647 100755
--- a/scripts/libtrim.pl
+++ b/scripts/libtrim.pl
@@ -10,188 +10,187 @@
open (LIB, $ARGV[1]) ;
my $prefix = $ARGV[0];
my @cells = (
-"xnor2_4",
-"dfstp_2",
-"xor3_4",
-"or2b_2",
-"xnor3_2",
-"sdfbbn_2",
-"sdfxtp_2",
-"dfxtp_2",
-"xor2_2",
-"o311ai_2",
-"nand2_2",
-"sdfrtp_2",
-"and4_2",
-"dfsbp_2",
-"or4_2",
-"inv_2",
-"dfrbp_2",
-"buf_8",
-"dlymetal6s4s_1",
-"xor2_4",
-"inv_4",
-"o31ai_2",
-"bufbuf_16",
-"dlygate4sd3_1",
-"o22ai_2",
-"o32ai_2",
-"and3_2",
-"o2111ai_2",
-"dlrbp_2",
-"and4bb_2",
-"nand3b_2",
-"buf_6",
-"and4b_2",
-"a2bb2oi_2",
-"buf_12",
-"and2_2",
-"dlxbn_2",
-"dlrtp_2",
-"xor3_1",
-"a21oi_2",
-"inv_12",
-"o21ai_2",
-"a311oi_2",
-"buf_4",
-"o21bai_2",
-"nand3_2",
-"dlygate4sd2_1",
-"o211ai_2",
-"or4b_2",
-"and3b_2",
-"or4bb_2",
-"sdfrbp_2",
-"o2bb2ai_2",
-"bufinv_16",
-"xor3_2",
-"o41ai_2",
-"or3b_2",
-"inv_8",
-"or2_2",
-"dfrtp_2",
-"bufbuf_8",
-"bufinv_8",
-"buf_16",
-"buf_2",
-"inv_6",
-"xnor3_4",
-"inv_16",
-"and2b_2",
-"a2111oi_2",
-"dfxbp_2",
-"xnor3_1",
-"dlymetal6s6s_1",
-"dfbbn_2",
-"o221ai_2",
-"sdfstp_2",
-"a31oi_2",
-"a211oi_2",
-"nand2b_2",
-"a22oi_2",
-"dlymetal6s2s_1",
-"dlxtn_2",
-"a21boi_2",
-"dlrtn_2",
-"a221oi_2",
-"or3_2",
-"sdfsbp_2",
-"xnor2_2",
-"sdfxbp_2"
-# # conb - 1
-# 'conb_1',
-#
-# # AND - 9
-# 'and2_1','and2_2','and2_4',
-# 'and3_1','and3_2','and3_4',
-# 'and4_1','and4_2','and4_4',
-#
-# # Buffer - 5
-# 'buf_1','buf_2','buf_4','buf_8','buf_16',
-#
-# # Clock Buffer - 5
-# #'clkbuf_1','clkbuf_2','clkbuf_4','clkbuf_8','clkbuf_16',
-#
-# # Inverters - 5
-# 'inv_1','inv_2','inv_4','inv_8','inv_16',
-#
-# # Majority - 3
-# 'maj3_1','maj3_2','maj3_4',
-#
-# # Multiplexors - 10
-# 'mux2_1','mux2_2','mux2_4','mux2_8',
-# 'mux2i_1','mux2i_2','mux2i_4',
-# 'mux4_1','mux4_2','mux4_4',
-#
-# # NAND - 10
-# 'nand2_1','nand2_2','nand2_4','nand2_8',
-# 'nand3_1','nand3_2','nand3_4',
-# 'nand4_1','nand4_2','nand4_4',
-#
-# # NOR - 10
-# 'nor2_1','nor2_2','nor2_4','nor2_8',
-# 'nor3_1','nor3_2','nor3_4',
-# 'nor4_1','nor4_2','nor4_4',
-#
-# # OR - 9
-# 'or2_1','or2_2','or2_4',
-# 'or3_1','or3_2','or3_4',
-# 'or4_1','or4_2','or4_4',
-#
-# # XOR - 4
-# 'xor2_1','xor2_2','xor2_4',
-# 'xor3_1',
-#
-# # XNOR - 4
-# 'xnor2_1','xnor2_2','xnor2_4',
-# 'xnor3_1',
-#
-# # OA & OAI - 24
-# 'o41a_1', 'o41a_2', 'o41a_4',
-# 'o41ai_1', 'o41ai_2', 'o41ai_4',
-# 'o32a_1', 'o32a_2', 'o32a_4',
-# 'o32ai_1', 'o32ai_2', 'o32ai_4',
-# #'o22a_1',
-# 'o22a_2', 'o22a_4',
-# #'o22ai_1',
-# 'o22ai_2', 'o22ai_4',
-# #'o21a_1',
-# 'o21a_2', 'o21a_4',
-# #'o21ai_1',
-# 'o21ai_2', 'o21ai_4',
-#
-# # AO & AOI - 48
-# 'a41o_1', 'a41o_2', 'a41o_4',
-# 'a41oi_1', 'a41oi_2', 'a41oi_4',
-#
-# 'a32o_1', 'a32o_2', 'a32o_4',
-# 'a32oi_1', 'a32oi_2', 'a32oi_4',
-#
-# 'a22o_1', 'a22o_2', 'a22o_4',
-# 'a22oi_1', 'a22oi_2', 'a22oi_4',
-# 'a21o_1', 'a21o_2', 'a21o_4',
-# 'a21bo_1', 'a21bo_2', 'a21bo_4',
-# 'a21oi_1', 'a21oi_2', 'a21oi_4',
-# 'a21boi_1', 'a21boi_2', 'a21boi_4',
-# 'a2111o_1', 'a2111o_2', 'a2111o_4',
-# 'a2111oi_1', 'a2111oi_2', 'a2111oi_4',
-# 'a211o_1', 'a211o_2', 'a211o_4',
-# 'a211oi_1', 'a211oi_2', 'a211oi_4',
-#
-# 'a2bb2oi_1', 'a2bb2oi_2', 'a2bb2oi_4'.
-# 'a2bb2o_1', 'a2bb2o_2', 'a2bb2o_4'.
-#
-# # FF - 20
-# 'dfrtn_1',
-# 'dfbbn_1', 'dfbbn_2',
-# 'dfbbp_1',
-# 'dfxbp_1', 'dfxbp_2',
-# 'edfxbp_1',
-# 'dfxtp_1', 'dfxtp_2', 'dfxtp_4',
-# 'dfrbp_1', 'dfrbp_2',
-# 'dfrtp_1', 'dfrtp_2', 'dfrtp_4',
-# 'dfsbp_1', 'dfsbp_2',
-# 'dfstp_1', 'dfstp_2', 'dfstp_4',
+# "xnor2_4",
+# "dfstp_2",
+# "xor3_4",
+# "or2b_2",
+# "xnor3_2",
+# "sdfbbn_2",
+# "sdfxtp_2",
+# "dfxtp_2",
+# "xor2_2",
+# "o311ai_2",
+# "nand2_2",
+# "sdfrtp_2",
+# "and4_2",
+# "dfsbp_2",
+# "or4_2",
+# "inv_2",
+# "dfrbp_2",
+# "buf_8",
+# "dlymetal6s4s_1",
+# "xor2_4",
+# "inv_4",
+# "o31ai_2",
+# "bufbuf_16",
+# "dlygate4sd3_1",
+# "o22ai_2",
+# "o32ai_2",
+# "and3_2",
+# "o2111ai_2",
+# "dlrbp_2",
+# "and4bb_2",
+# "nand3b_2",
+# "buf_6",
+# "and4b_2",
+# "a2bb2oi_2",
+# "buf_12",
+# "and2_2",
+# "dlxbn_2",
+# "dlrtp_2",
+# "xor3_1",
+# "a21oi_2",
+# "inv_12",
+# "o21ai_2",
+# "a311oi_2",
+# "buf_4",
+# "o21bai_2",
+# "nand3_2",
+# "dlygate4sd2_1",
+# "o211ai_2",
+# "or4b_2",
+# "and3b_2",
+# "or4bb_2",
+# "sdfrbp_2",
+# "o2bb2ai_2",
+# "bufinv_16",
+# "xor3_2",
+# "o41ai_2",
+# "or3b_2",
+# "inv_8",
+# "or2_2",
+# "dfrtp_2",
+# "bufbuf_8",
+# "bufinv_8",
+# "buf_16",
+# "buf_2",
+# "inv_6",
+# "xnor3_4",
+# "inv_16",
+# "and2b_2",
+# "a2111oi_2",
+# "dfxbp_2",
+# "xnor3_1",
+# "dlymetal6s6s_1",
+# "dfbbn_2",
+# "o221ai_2",
+# "sdfstp_2",
+# "a31oi_2",
+# "a211oi_2",
+# "nand2b_2",
+# "a22oi_2",
+# "dlymetal6s2s_1",
+# "dlxtn_2",
+# "a21boi_2",
+# "dlrtn_2",
+# "a221oi_2",
+# "or3_2",
+# "sdfsbp_2",
+# "xnor2_2",
+# "sdfxbp_2"
+ # conb - 1
+ 'conb_1',
+
+ # AND - 9
+ 'and2_4',
+ 'and3_4',
+ 'and4_4',
+
+ # Buffer - 5
+ 'buf_8','buf_16',
+
+ # Clock Buffer - 5
+ #'clkbuf_1','clkbuf_2','clkbuf_4','clkbuf_8','clkbuf_16',
+
+ # Inverters - 5
+ 'inv_8','inv_16',
+
+ # Majority - 3
+ 'maj3_4',
+
+ # Multiplexors - 10
+ 'mux2_8',
+ 'mux2i_4',
+ 'mux4_4',
+
+ # NAND - 10
+ 'nand2_4','nand2_8',
+ 'nand3_4',
+ 'nand4_4',
+
+ # NOR - 10
+ 'nor2_4','nor2_8',
+ 'nor3_4',
+ 'nor4_4',
+
+ # OR - 9
+ 'or2_4',
+ 'or3_4',
+ 'or4_4',
+
+ # XOR - 4
+ 'xor2_4',
+
+
+ # XNOR - 4
+ 'xnor2_4',
+
+ # OA & OAI - 24
+ 'o41a_4',
+ 'o41ai_4',
+ 'o32a_4',
+ 'o32ai_4',
+ #'o22a_1',
+ 'o22a_4',
+ #'o22ai_1',
+ 'o22ai_4',
+ #'o21a_1',
+ 'o21a_4',
+ #'o21ai_1',
+ 'o21ai_4',
+
+ # AO & AOI - 48
+ 'a41o_4',
+ 'a41oi_4',
+
+ 'a32o_4',
+ 'a32oi_4',
+
+ 'a22o_3',
+ 'a22oi_4',
+ 'a21o_4',
+ 'a21bo_4',
+ 'a21oi_4',
+ 'a21boi_4',
+ 'a2111o_4',
+ 'a2111oi_4',
+ 'a211o_4',
+ 'a211oi_4',
+
+ 'a2bb2oi_4'.
+ 'a2bb2o_4'.
+
+ # FF - 20
+
+ 'dfbbn_2',
+
+ 'dfxbp_2',
+
+ 'dfxtp_4',
+ 'dfrbp_2',
+ 'dfrtp_4',
+
+ 'dfstp_4',
);
diff --git a/scripts/padLefMacro.py b/scripts/padLefMacro.py
index 4d2f970..274f974 100755
--- a/scripts/padLefMacro.py
+++ b/scripts/padLefMacro.py
@@ -9,16 +9,16 @@
# ==============================================================================
parser = argparse.ArgumentParser(
description='Adds padding to the right of all macros in a lef file')
-parser.add_argument('--right', '-r', required=False, type=int,
+parser.add_argument('--right', '-r', required=False, type=float,
default='0',
help='Padding on the right in SITE widths')
-parser.add_argument('--left', '-l', required=False, type=int,
+parser.add_argument('--left', '-l', required=False, type=float,
default='0',
help='Padding on the left in SITE widths')
-parser.add_argument('--top', '-t', required=False, type=int,
+parser.add_argument('--top', '-t', required=False, type=float,
default='0',
help='Padding on the top in SITE heights')
-parser.add_argument('--bottom', '-b', required=False, type=int,
+parser.add_argument('--bottom', '-b', required=False, type=float,
default='0',
help='Padding on the bottom in SITE heights')
parser.add_argument('--site', '-s', required=False,
diff --git a/scripts/run_magic.tcl b/scripts/run_magic.tcl
index b125f13..a1797a4 100644
--- a/scripts/run_magic.tcl
+++ b/scripts/run_magic.tcl
@@ -1,7 +1,7 @@
set magicrc $::env(TMP_DIR)/magic.magicrc
set ::env(PDKPATH) "$::env(PDK_ROOT)/ef-skywater-s8/EFS8A"
set ::env(MAGPATH) "$::env(PDKPATH)/libs.ref/maglef"
-exec envsubst < $::env(SCRIPTS_DIR)/tmp.magicrc > $magicrc
+exec envsubst < $::env(MAGIC_MAGICRC) > $magicrc
exec magic \
-noconsole \
-dnull \
diff --git a/scripts/tcl_commands/all.tcl b/scripts/tcl_commands/all.tcl
index 0672a65..f4de39b 100644
--- a/scripts/tcl_commands/all.tcl
+++ b/scripts/tcl_commands/all.tcl
@@ -176,7 +176,7 @@
# pad lef
set ::env(CELLS_LEF_UNPADDED) $::env(TMP_DIR)/merged_unpadded.lef
- try_catch $::env(SCRIPTS_DIR)/padLefMacro.py -s $::env(PLACE_SITE) -r $::env(CELL_PAD) -i $::env(CELLS_LEF_UNPADDED) -o $::env(TMP_DIR)/merged.lef -e $::env(CELL_PAD_EXECLUDE)
+ try_catch $::env(SCRIPTS_DIR)/padLefMacro.py -s $::env(PLACE_SITE) -r $::env(CELL_PAD) -i $::env(CELLS_LEF_UNPADDED) -o $::env(TMP_DIR)/merged.lef -e "$::env(CELL_PAD_EXECLUDE)" |& tee $::env(TERMINAL_OUTPUT)
set ::env(CELLS_LEF) $::env(TMP_DIR)/merged.lef
if { $::env(USE_GPIO_PADS) } {
@@ -188,9 +188,14 @@
# trim libs
set trimmed_lib $::env(TMP_DIR)/trimmed.lib
- puts $::env(LIB_SYNTH)
- exec $::env(SCRIPTS_DIR)/libtrim.pl $::env(PDK_VARIANT) $::env(LIB_SYNTH) > $trimmed_lib
- set ::env(LIB_SYNTH) $trimmed_lib
+ if { ![info exists $trimmed_lib] } {
+ puts $::env(LIB_SYNTH)
+ exec $::env(SCRIPTS_DIR)/libtrim.pl $::env(PDK_VARIANT) $::env(LIB_SYNTH) > $trimmed_lib
+ set ::env(LIB_SYNTH) $trimmed_lib
+ }
+
+ set tracks_copy $::env(TMP_DIR)/tracks_copy.info
+ exec cp $::env(TRACKS_INFO_FILE) $tracks_copy
# change to system verilog
#if {$::env(SYSTEM_VERILOG)} {
@@ -215,6 +220,7 @@
set_log ::env(CELL_PAD) $::env(CELL_PAD) $::env(GLB_CFG_FILE) 1
set_log ::env(MERGED_LEF) $::env(MERGED_LEF) $::env(GLB_CFG_FILE) 1
set_log ::env(TRACKS_INFO_FILE) $::env(TRACKS_INFO_FILE) $::env(GLB_CFG_FILE) 1
+ set_log ::env(TECH_LEF) $::env(TECH_LEF) $::env(GLB_CFG_FILE) 1
# Design
exec echo "# Design config" >> $::env(GLB_CFG_FILE)
set_log ::env(CLOCK_PERIOD) $::env(CLOCK_PERIOD) $::env(GLB_CFG_FILE) 1
@@ -356,10 +362,14 @@
}
proc run_magic_drc {args} {
+ set magicrc $::env(TMP_DIR)/magic.magicrc
+ set ::env(PDKPATH) "$::env(PDK_ROOT)/ef-skywater-s8/EFS8A"
+ set ::env(MAGPATH) "$::env(PDKPATH)/libs.ref/maglef"
+ exec envsubst < $::env(MAGIC_MAGICRC) > $magicrc
exec magic \
-noconsole \
-dnull \
- -rcfile $::env(TMP_DIR)/magic.magicrc \
+ -rcfile $magicrc \
$::env(SCRIPTS_DIR)/magic_drc.tcl \
</dev/null \
|& tee $::env(TERMINAL_OUTPUT) $::env(magic_log_file_tag)_drc.log
diff --git a/scripts/tmp.magicrc b/scripts/tmp.magicrc
deleted file mode 100644
index 246beb3..0000000
--- a/scripts/tmp.magicrc
+++ /dev/null
@@ -1,53 +0,0 @@
-puts stdout "Sourcing design .magicrc for technology EFS8A ..."
-
-# Put grid on 0.005 pitch. This is important, as some commands don't
-# rescale the grid automatically (such as lef read?).
-
-#set scalefac [tech lambda]
-if {[lindex [tech lambda] 1] < 2} {
- scalegrid 1 2
-}
-
-# drc off
-drc euclidean on
-
-#set PDKPATH "${PDK_ROOT}/pdks/ef-skywater-s8/EFS8A"
-
-# loading technology
-tech load $PDKPATH/libs.tech/magic/current/EFS8A.tech
-
-
-# load techlef ?
-lef read ${TECH_LEF}
-
-# load device generator
-source $PDKPATH/libs.tech/magic/current/EFS8A.tcl
-
-# load bind keys (optional)
-source $PDKPATH/libs.tech/magic/current/EFS8A-BindKeys
-
-# set units to lambda grid
-snap lambda
-
-# add path to reference cells
-#set MAGPATH "${PDKPATH}/libs.ref/maglef"
-addpath ${MAGPATH}/primdev
-addpath ${MAGPATH}/s8_osu130
-addpath ${MAGPATH}/efs8hd
-addpath ${MAGPATH}/efs8_pads
-#addpath ${MAGPATH}/s8fmlt
-#addpath ${MAGPATH}/s8iom0
-#addpath ${MAGPATH}/scs8hd
-#addpath ${MAGPATH}/scs8hdll
-#addpath ${MAGPATH}/scs8hvl
-#addpath ${MAGPATH}/scs8hs
-#addpath ${MAGPATH}/scs8ms
-#addpath ${MAGPATH}/scs8ls
-#addpath ${MAGPATH}/scs8lp
-
-# add path to GDS cells
-
-# add path to IP from catalog. This procedure defined in the PDK script.
-catch {magic::query_mylib_ip}
-# add path to local IP from user design space. Defined in the PDK script.
-catch {magic::query_my_projects}
