// Verilog netlists of efs8_pads simple I/O library
//
// 1st draft, for I/O only;  no functional/behavioral description

`timescale 1ns/1ps

(* blackbox *)
module pad_spacer_1um (VDD1V8, VSS, VDD3V3, VSSIO, VDDIO);
    inout VDD1V8;
    inout VSS;
    inout VDD3V3;
    inout VSSIO;
    inout VDDIO;

endmodule

(* blackbox *)
module pad_spacer_2um (VDD1V8, VSS, VDD3V3, VSSIO, VDDIO);
    inout VDD1V8;
    inout VSS;
    inout VDD3V3;
    inout VSSIO;
    inout VDDIO;

endmodule

(* blackbox *)
module pad_spacer_5um (VDD1V8, VSS, VDD3V3, VSSIO, VDDIO);
    inout VDD1V8;
    inout VSS;
    inout VDD3V3;
    inout VSSIO;
    inout VDDIO;

endmodule

(* blackbox *)
module pad_spacer_10um (VDD1V8, VSS, VDD3V3, VSSIO, VDDIO);
    inout VDD1V8;
    inout VSS;
    inout VDD3V3;
    inout VSSIO;
    inout VDDIO;

endmodule

(* blackbox *)
module pad_spacer_20um (VDD1V8, VSS, VDD3V3, VSSIO, VDDIO);
    inout VDD1V8;
    inout VSS;
    inout VDD3V3;
    inout VSSIO;
    inout VDDIO;

endmodule

(* blackbox *)
module pad_spacer_50um (VDD1V8, VSS, VDD3V3, VSSIO, VDDIO);
    inout VDD1V8;
    inout VSS;
    inout VDD3V3;
    inout VSSIO;
    inout VDDIO;

endmodule

(* blackbox *)
module corner_pad (VDD1V8, VSS, VDD3V3, VSSIO, VDDIO);
    inout VDD1V8;
    inout VSS;
    inout VDD3V3;
    inout VSSIO;
    inout VDDIO;

endmodule

(* blackbox *)
module vdd1v8_pad (VDD1V8, VSS, VDD3V3, VSSIO, VDDIO);
    inout VDD1V8;
    inout VSS;
    inout VDD3V3;
    inout VSSIO;
    inout VDDIO;

endmodule

(* blackbox *)
module vdd3v3_pad (VDD1V8, VSS, VDD3V3, VSSIO, VDDIO);
    inout VDD1V8;
    inout VSS;
    inout VDD3V3;
    inout VSSIO;
    inout VDDIO;

endmodule

(* blackbox *)
module vss_pad (VDD1V8, VSS, VDD3V3, VSSIO, VDDIO);
    inout VDD1V8;
    inout VSS;
    inout VDD3V3;
    inout VSSIO;
    inout VDDIO;

endmodule

(* blackbox *)
module vddio_pad (VDD1V8, VSS, VDD3V3, VSSIO, VDDIO);
    inout VDD1V8;
    inout VSS;
    inout VDD3V3;
    inout VSSIO;
    inout VDDIO;

endmodule

(* blackbox *)
module vssio_pad (VDD1V8, VSS, VDD3V3, VSSIO, VDDIO);
    inout VDD1V8;
    inout VSS;
    inout VDD3V3;
    inout VSSIO;
    inout VDDIO;

endmodule

(* blackbox *)
module digital_in_pad (VDD1V8, VSS, VDD3V3, VSSIO, VDDIO, PAD, in, in3v);
    inout VDD1V8;
    inout VSS;
    inout VDD3V3;
    inout VSSIO;
    inout VDDIO;
    input PAD;
    input in;
    output in3v;

endmodule

(* blackbox *)
module digital_out_pad (VDD1V8, VSS, VDD3V3, VSSIO, VDDIO, PAD, out, in3v, pullupb, pulldownb, outenb, in);
    inout VDD1V8;
    inout VSS;
    inout VDD3V3;
    inout VSSIO;
    inout VDDIO;
    inout PAD;
    output out;
    output in3v;
    input pullupb;
    input pulldownb;
    input outenb;
    input in;

endmodule

(* blackbox *)
module analog_pad (VDD1V8, VSS, VDD3V3, VSSIO, VDDIO, PAD);
    inout VDD1V8;
    inout VSS;
    inout VDD3V3;
    inout VSSIO;
    inout VDDIO;
    inout PAD;

endmodule

(* blackbox *)
module analog200ohm_pad (VDD1V8, VSS, VDD3V3, VSSIO, VDDIO, PAD);
    inout VDD1V8;
    inout VSS;
    inout VDD3V3;
    inout VSSIO;
    inout VDDIO;
    inout PAD;

endmodule