| commit | 2c5336ee97194f0c77c746c8f08274dae743c4a0 | [log] [tgz] |
|---|---|---|
| author | Kareem Farid <kareem.farid@efabless.com> | Fri Feb 28 05:41:48 2020 -0800 |
| committer | Kareem Farid <kareem.farid@efabless.com> | Fri Feb 28 05:41:48 2020 -0800 |
| tree | 824183c1f688cde1e1150b87e8a6a85f996967f9 | |
| parent | 96124a9260ef8c842a5fde818c5382acaa8d7efb [diff] |
rename openstrive_soc to strive_soc
diff --git a/designs/openstriVe_soc/config.tcl b/designs/striVe_soc/config.tcl similarity index 78% rename from designs/openstriVe_soc/config.tcl rename to designs/striVe_soc/config.tcl index 44b47e8..660f280 100644 --- a/designs/openstriVe_soc/config.tcl +++ b/designs/striVe_soc/config.tcl
@@ -1,6 +1,6 @@ -set ::env(DESIGN_NAME) "openstriVe_soc" +set ::env(DESIGN_NAME) "striVe_soc" -set ::env(VERILOG_FILES) "./designs/openstriVe_soc/src/openstriVe_soc.v" +set ::env(VERILOG_FILES) "./designs/striVe_soc/src/striVe_soc.v" set ::env(CLOCK_PERIOD) "10" # which clock port ??
diff --git a/designs/openstriVe_soc/src/picorv32.v b/designs/striVe_soc/src/picorv32.v similarity index 100% rename from designs/openstriVe_soc/src/picorv32.v rename to designs/striVe_soc/src/picorv32.v
diff --git a/designs/openstriVe_soc/src/simpleuart.v b/designs/striVe_soc/src/simpleuart.v similarity index 100% rename from designs/openstriVe_soc/src/simpleuart.v rename to designs/striVe_soc/src/simpleuart.v
diff --git a/designs/openstriVe_soc/src/spimemio.v b/designs/striVe_soc/src/spimemio.v similarity index 100% rename from designs/openstriVe_soc/src/spimemio.v rename to designs/striVe_soc/src/spimemio.v
diff --git a/designs/openstriVe_soc/src/striVe_soc.v b/designs/striVe_soc/src/striVe_soc.v similarity index 99% rename from designs/openstriVe_soc/src/striVe_soc.v rename to designs/striVe_soc/src/striVe_soc.v index 6cdbe00..9fe97d8 100644 --- a/designs/openstriVe_soc/src/striVe_soc.v +++ b/designs/striVe_soc/src/striVe_soc.v
@@ -37,7 +37,7 @@ `define PICORV32_REGS openstriVe_soc_regs -module openstriVe_soc ( +module striVe_soc ( `ifdef LVS inout vdd1v8, /* 1.8V domain */ inout vss,