set ::env(DESIGN_NAME) "raven_soc"

set ::env(VERILOG_FILES) "./designs/raven_soc/src/raven_soc.v"

set ::env(CLOCK_PERIOD) "14"
# which clock port ??
set ::env(CLOCK_PORT) "ext_clk" 

set ::env(FP_CORE_MARGIN) 3.36
set ::env(SYNTH_STRAT) 2