set ::env(DESIGN_NAME) "aes_core"

set ::env(VERILOG_FILES) "./designs/aes_core/src/aes.v"
set ::env(SDC_FILE) "./designs/$::env(DESIGN_NAME)/src/$::env(DESIGN_NAME).sdc"

set ::env(CLOCK_PERIOD) "5.000"
set ::env(CLOCK_PORT) "clk"

set ::env(FP_CORE_UTIL) 40
set ::env(PL_TARGET_DENSITY) 0.4
set ::env(GLB_RT_ADJUSTMENT) 0.15