* CACE gensim simulation file ${FILENAME}_${N}
* Generated by CACE gensim, efabless inc. (c) 2017

.lib "/ef/tech/SW/EFS8A/libs.tech/ngspice/s8.lib" ${CORNER}

.option TEMP = ${TEMPERATURE}

.include "${DUT_PATH}"

XDUT ${PIN:A:A} ${PIN:X:X}
+${PIN:VDD3V3:VDD3V3} ${PIN:VDD1V8:VDD1V8} ${PIN:VSS:VSS} ${DUT_NAME}

VVIN A VSS DC 0 PWL (
+ 0 ${VOLTAGE:VSS} 500n ${VOLTAGE:VSS} 501n ${VOLTAGE:VDD1V8} 1u ${VOLTAGE:VDD1V8})
* Device is unloaded for prop delay test
* RLOAD OUT 0 ${RESISTANCE:X}
* CLOAD OUT 0 ${CAPACITANCE:X}
VVDD33 VDD3V3 VSS DC ${VOLTAGE:VDD3V3}
VVDD18 VDD1V8 VSS DC ${VOLTAGE:VDD1V8}
VVSS VSS 0 DC ${VOLTAGE:VSS}

* Propagation delay.  Input differential (VOLTAGE:VDIFF) is set to the
* overdrive voltage.  Set this to the low value, then switch
* to the high.  Measure the time for the output to change state
* (cross VDDA / 2).

.control
tran 1e-9 1e-6
meas tran trise WHEN V(X) = ${VOLTAGE:VDD3V3} 2 ${/} CROSS=1
let tpd = $&trise - 500e-9
echo "${FILENAME} = ", "$&tpd"
quit
.endc
.end