* Digital PLL

.include "digital_pll_controller.xspice"
.include "ring_osc2x13.spi"

.subckt digital_pll reset osc clkp0 clkp1 div0 div1 div2 div3 div4 clkd2
+ clkd4 clkd8 clkd16 vdd vss

X0 vdd vss clkp0 div0 div1 div2 div3 div4 osc reset trim0 trim1 trim2 trim3
+ trim4 trim5 trim6 trim7 trim8 trim9 trim10 trim11 trim12 trim13 trim14
+ trim15 trim16 trim17 trim18 trim19 trim20 trim21 trim22 trim23 trim24
+ trim25 digital_pll_controller

X1 vdd vss clkp0 clkp1 reset trim0 trim1 trim2 trim3 trim4 trim5 trim6 trim7
+ trim8 trim9 trim10 trim11 trim12 trim13 trim14 trim15 trim16 trim17 trim18
+ trim19 trim20 trim21 trim22 trim23 trim24 trim25 ring_osc2x13

X2 reset resetb vss vss vdd vdd scs8ms_inv_4

* Create divided down clocks.  The inverted output only comes
* with digital standard cells with inverted resets, so the
* reset has to be inverted as well.

X3 clkp1 clkd2 int0 clkd2 resetb vss vss vdd vdd scs8ms_dfrbp_1
X4 clkd2 clkd4 int1 clkd4 resetb vss vss vdd vdd scs8ms_dfrbp_1
X5 clkd4 clkd8 int2 clkd8 resetb vss vss vdd vdd scs8ms_dfrbp_1
X6 clkd8 clkd16 int3 clkd16 resetb vss vss vdd vdd scs8ms_dfrbp_1

.ends