Merge branch 'master' of gitlab.com:efabless/designs/strive
diff --git a/mag/lvlshiftdown_abstract.lef b/mag/lvlshiftdown_abstract.lef
new file mode 120000
index 0000000..1270878
--- /dev/null
+++ b/mag/lvlshiftdown_abstract.lef
@@ -0,0 +1 @@
+lvlshiftdown.lef
\ No newline at end of file
diff --git a/mag/lvlshiftdown_full.lef b/mag/lvlshiftdown_full.lef
new file mode 100644
index 0000000..a158981
--- /dev/null
+++ b/mag/lvlshiftdown_full.lef
@@ -0,0 +1,121 @@
+VERSION 5.3 ;
+ NAMESCASESENSITIVE ON ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+UNITS
+ DATABASE MICRONS 1000 ;
+END UNITS
+
+MACRO lvlshiftdown
+ CLASS BLOCK ;
+ FOREIGN lvlshiftdown ;
+ ORIGIN -0.0000 -0.0000 ;
+ SIZE 9.6000 BY 4.0700 ;
+ PIN vnb
+ PORT
+ LAYER li1 ;
+ RECT 0.0000 -0.0850 9.6000 0.0850 ;
+ LAYER met1 ;
+ RECT 0.0000 -0.1150 9.6000 0.1150 ;
+ END
+ END vnb
+ PIN vpwr
+ PORT
+ LAYER li1 ;
+ RECT 0.6150 3.6250 9.5050 3.7950 ;
+ RECT 0.6150 2.4450 1.8650 3.6250 ;
+ RECT 2.7650 2.3850 3.4350 3.6250 ;
+ RECT 4.1050 2.3850 4.9950 3.6250 ;
+ RECT 5.6650 2.3850 6.5550 3.6250 ;
+ RECT 7.2250 2.3850 8.1150 3.6250 ;
+ RECT 8.9050 3.4750 9.5050 3.6250 ;
+ RECT 9.1350 2.3850 9.5050 3.4750 ;
+ LAYER met1 ;
+ RECT 0.0000 3.4450 9.6000 3.8150 ;
+ END
+ END vpwr
+ PIN vpb
+ PORT
+ LAYER li1 ;
+ RECT 0.0000 3.9850 9.6000 4.1550 ;
+ LAYER met1 ;
+ RECT 0.0000 3.9550 9.6000 4.1850 ;
+ END
+ END vpb
+ PIN vpb
+ END vpb
+ PIN vgnd
+ PORT
+ LAYER li1 ;
+ RECT 0.6750 0.5500 1.9250 1.3850 ;
+ RECT 2.7650 0.7600 3.4950 1.4450 ;
+ RECT 2.6050 0.5500 3.4950 0.7600 ;
+ RECT 4.0450 0.5500 5.0550 1.4450 ;
+ RECT 5.6050 0.5500 6.6150 1.4450 ;
+ RECT 7.1650 0.5500 8.1750 1.4450 ;
+ RECT 9.1350 0.6000 9.5050 1.4450 ;
+ RECT 8.9750 0.5500 9.5050 0.6000 ;
+ RECT 0.6750 0.3800 9.5050 0.5500 ;
+ LAYER met1 ;
+ RECT 0.0000 0.2550 9.6000 0.6250 ;
+ END
+ END vgnd
+ PIN vnb
+ END vnb
+ PIN X
+ PORT
+ LAYER li1 ;
+ RECT 3.6050 2.2050 3.9350 3.4450 ;
+ RECT 5.1650 2.2050 5.4950 3.4450 ;
+ RECT 6.7250 2.2050 7.0550 3.4450 ;
+ RECT 8.2850 3.2300 8.7350 3.4450 ;
+ RECT 8.2850 2.2050 8.9650 3.2300 ;
+ RECT 3.6050 2.0350 8.9650 2.2050 ;
+ RECT 3.6650 1.6250 8.5550 1.7950 ;
+ RECT 3.6650 0.8050 3.8750 1.6250 ;
+ RECT 5.2250 0.8050 5.4350 1.6250 ;
+ RECT 6.7850 0.8050 6.9950 1.6250 ;
+ RECT 8.3450 0.9750 8.5550 1.6250 ;
+ RECT 8.7350 0.9750 8.9650 2.0350 ;
+ RECT 8.3450 0.8050 8.9650 0.9750 ;
+ END
+ END X
+ PIN X
+ END X
+ PIN X
+ END X
+ PIN X
+ END X
+ PIN X
+ END X
+ PIN X
+ END X
+ PIN X
+ END X
+ PIN A
+ PORT
+ LAYER li1 ;
+ RECT 0.6350 1.5800 2.2450 1.8150 ;
+ END
+ END A
+ PIN A
+ END A
+ PIN A
+ END A
+ PIN A
+ END A
+ OBS
+ LAYER li1 ;
+ RECT 0.2450 2.2650 0.4350 3.5450 ;
+ RECT 2.0450 2.2650 2.5950 3.4450 ;
+ RECT 0.2450 2.0950 2.5950 2.2650 ;
+ RECT 0.2450 1.4750 0.4350 2.0950 ;
+ RECT 2.4250 1.9550 2.5950 2.0950 ;
+ RECT 2.4250 1.6250 3.3800 1.9550 ;
+ RECT 0.2450 0.8050 0.4550 1.4750 ;
+ RECT 2.4250 1.4000 2.5950 1.6250 ;
+ RECT 2.1050 1.2300 2.5950 1.4000 ;
+ RECT 2.1050 0.7300 2.3150 1.2300 ;
+ END
+END lvlshiftdown
diff --git a/mag/scs8hd_conb_1.lef b/mag/scs8hd_conb_1.lef
new file mode 100644
index 0000000..409849e
--- /dev/null
+++ b/mag/scs8hd_conb_1.lef
@@ -0,0 +1,56 @@
+VERSION 5.3 ;
+ NAMESCASESENSITIVE ON ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+UNITS
+ DATABASE MICRONS 1000 ;
+END UNITS
+
+MACRO scs8hd_conb_1
+ CLASS CORE ;
+ SOURCE USER ;
+ FOREIGN scs8hd_conb_1 ;
+ ORIGIN -0.0000 -0.0000 ;
+ SIZE 1.3800 BY 2.7200 ;
+ SYMMETRY X Y R90 ;
+ PIN HI
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 0.0850 0.2550 0.6050 1.7400 ;
+ END
+ END HI
+ PIN LO
+ DIRECTION OUTPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER li1 ;
+ RECT 0.7750 0.9150 1.2950 2.4650 ;
+ END
+ END LO
+ PIN vpwr
+ DIRECTION INOUT ;
+ USE POWER ;
+ PORT
+ LAYER met1 ;
+ RECT 0.0000 2.4800 1.3800 2.9600 ;
+ END
+ END vpwr
+ PIN vgnd
+ DIRECTION INOUT ;
+ USE GROUND ;
+ PORT
+ LAYER met1 ;
+ RECT 0.0000 -0.2400 1.3800 0.2400 ;
+ END
+ END vgnd
+ OBS
+ LAYER li1 ;
+ RECT 0.0000 2.6350 1.3800 2.8050 ;
+ RECT 0.2750 1.9100 0.6050 2.6350 ;
+ RECT 0.7750 0.0850 1.1150 0.7450 ;
+ RECT 0.0000 -0.0850 1.3800 0.0850 ;
+ END
+END scs8hd_conb_1
diff --git a/openlane/input/config_clkrst.tcl b/openlane/input/config_clkrst.tcl
deleted file mode 100644
index 46a0af4..0000000
--- a/openlane/input/config_clkrst.tcl
+++ /dev/null
@@ -1,15 +0,0 @@
-set script_dir [file dirname [file normalize [info script]]]
-set ::env(DESIGN_NAME) striVe_clkrst
-
-# Change if needed
-set ::env(VERILOG_FILES) $script_dir/../../verilog/rtl/striVe_clkrst.v
-set ::env(SYNTH_SCRIPT) $script_dir/synth_scripts/synth.tcl
-
-# Fill this
-set ::env(CLOCK_PERIOD) "50"
-set ::env(CLOCK_PORT) "ext_clk"
-
-set ::env(CLOCK_NET) "clk"
-set ::env(RUN_SIMPLE_CTS) 0
-set ::env(PL_INITIAL_PLACEMENT) 1
-
diff --git a/openlane/input/config_pll.tcl b/openlane/input/digital_pll/config.tcl
similarity index 85%
rename from openlane/input/config_pll.tcl
rename to openlane/input/digital_pll/config.tcl
index e57a5b9..474ee3a 100644
--- a/openlane/input/config_pll.tcl
+++ b/openlane/input/digital_pll/config.tcl
@@ -1,6 +1,6 @@
set script_dir [file dirname [file normalize [info script]]]
set ::env(DESIGN_NAME) digital_pll
-set ::env(VERILOG_FILES) $script_dir/../../verilog/rtl/digital_pll.v
+set ::env(VERILOG_FILES) $script_dir/../../../verilog/rtl/digital_pll.v
# Fill this
set ::env(CLOCK_PERIOD) "100000"
diff --git a/openlane/input/striVe/config.tcl b/openlane/input/striVe/config.tcl
new file mode 100644
index 0000000..a3120a3
--- /dev/null
+++ b/openlane/input/striVe/config.tcl
@@ -0,0 +1,26 @@
+# User config
+set script_dir [file dirname [file normalize [info script]]]
+set ::env(DESIGN_NAME) striVe
+
+set verilog_root $script_dir/../../../verilog/rtl/
+# Change if needed
+set ::env(VERILOG_FILES) $verilog_root/striVe_nopwr_nocorner.v
+set ::env(VERILOG_FILES_BLACKBOX) "$verilog_root/striVe_soc.v $verilog_root/striVe_spi.v $verilog_root/digital_pll.v $verilog_root/striVe_clkrst.v $verilog_root/lvlshiftdown.v"
+
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+
+
+# Fill this
+set ::env(CLOCK_PERIOD) "50"
+set ::env(CLOCK_PORT) "xclk"
+
+set ::env(USE_GPIO_PADS) 1
+set ::env(RUN_SIMPLE_CTS) 0
+set ::env(FILL_INSERTION) 0
+set ::env(SYNTH_TOP_LEVEL) 1
+set ::env(CELL_PAD) 0
+set ::env(MAGIC_PAD) 0
+set ::env(MAGIC_ZEROIZE_ORIGIN) 0
+
+#set ::env(EXTRA_LEFS) [glob $::env(DESIGN_DIR)/src/mag/*.lef]
+#set ::env(EXTRA_GDS_FILES) [glob $::env(DESIGN_DIR)/src/mag/*.gds]
diff --git a/openlane/input/striVe/interactive.tcl b/openlane/input/striVe/interactive.tcl
new file mode 100644
index 0000000..50ee847
--- /dev/null
+++ b/openlane/input/striVe/interactive.tcl
@@ -0,0 +1,51 @@
+package require openlane
+set script_dir [file dirname [file normalize [info script]]]
+prep -design $script_dir -tag striVe -run_path $script_dir/../../runs/ -overwrite
+
+#config
+
+
+set macros "digital_pll striVe_spi striVe_clkrst striVe_soc lvlshiftdown"
+set lefs_root $script_dir/../../../mag/
+set padframe_root $::env(TMP_DIR)/padframe/striVe/
+set verilog_root $script_dir/../../../verilog/rtl/
+set stubs_root $script_dir/../../../verilog/stubs/
+set top_rtl $script_dir/../../../verilog/rtl/striVe.v
+set lefs {}
+
+exec mkdir -p $padframe_root/mag
+exec mkdir -p $padframe_root/verilog
+file copy -force $top_rtl $padframe_root/verilog/
+puts "$macros"
+foreach macro "$macros" {
+ file copy -force $lefs_root/${macro}_abstract.lef $padframe_root/mag/$macro.lef
+ file copy -force $verilog_root/${macro}.v $padframe_root/verilog/
+ lappend lefs $lefs_root/${macro}_abstract.lef
+}
+# need not to hard code this
+lappend lefs $lefs_root/scs8hd_conb_1.lef
+file copy -force $lefs_root/scs8hd_conb_1.lef $padframe_root/mag/
+
+foreach stub "[glob $stubs_root/*.v]" {
+ file copy -force $stub $padframe_root/verilog/
+}
+
+set padframe_cfg $padframe_root/mag/padframe.cfg
+set padframe_def $padframe_root/mag/padframe.def
+set core_def $padframe_root/mag/core.def
+padframe_gen -folder $padframe_root
+set area [padframe_extract_area -cfg $padframe_cfg]
+set ::env(DIE_AREA) $area
+set ::env(CORE_AREA) $area
+set ::env(FP_SIZING) absolute
+
+add_lefs -src $lefs
+verilog_elaborate
+# verilog2def for nets
+chip_floorplan
+merge_components -input1 $padframe_def -input2 $core_def -output $::env(CURRENT_DEF)
+run_routing
+exit
+set $::env(EXTRA_LEFS) $lefs
+run_magic
+run_magic_drc
diff --git a/openlane/input/striVe_clkrst/config.tcl b/openlane/input/striVe_clkrst/config.tcl
new file mode 100644
index 0000000..4170fc6
--- /dev/null
+++ b/openlane/input/striVe_clkrst/config.tcl
@@ -0,0 +1,22 @@
+set script_dir [file dirname [file normalize [info script]]]
+set ::env(DESIGN_NAME) striVe_clkrst
+
+# Change if needed
+set ::env(VERILOG_FILES) $script_dir/../../../verilog/rtl/striVe_clkrst.v
+set ::env(SYNTH_SCRIPT) $script_dir/synth.tcl
+
+# Fill this
+set ::env(CLOCK_PERIOD) "50"
+set ::env(CLOCK_PORT) "ext_clk"
+
+set ::env(CLOCK_NET) "clk"
+set ::env(RUN_SIMPLE_CTS) 0
+set ::env(PL_INITIAL_PLACEMENT) 1
+
+#set ::env(FP_CORE_UTIL) 35
+set ::env(FP_CORE_MARGIN) 0
+
+set ::env(FP_PDN_VOFFSET) 8
+set ::env(FP_PDN_VPITCH) 15
+set ::env(FP_PDN_HOFFSET) 8
+set ::env(FP_PDN_HPITCH) 15
diff --git a/openlane/input/synth_scripts/synth.tcl b/openlane/input/striVe_clkrst/synth.tcl
similarity index 100%
rename from openlane/input/synth_scripts/synth.tcl
rename to openlane/input/striVe_clkrst/synth.tcl
diff --git a/openlane/input/config_soc.tcl b/openlane/input/striVe_soc/config.tcl
similarity index 82%
rename from openlane/input/config_soc.tcl
rename to openlane/input/striVe_soc/config.tcl
index b6dc511..81c273e 100644
--- a/openlane/input/config_soc.tcl
+++ b/openlane/input/striVe_soc/config.tcl
@@ -1,5 +1,5 @@
set script_dir [file dirname [file normalize [info script]]]
-set ::env(VERILOG_FILES) $script_dir/../../verilog/rtl/striVe_soc.v
+set ::env(VERILOG_FILES) $script_dir/../../../verilog/rtl/striVe_soc.v
set ::env(DESIGN_NAME) "striVe_soc"
set ::env(CLOCK_PERIOD) "10"
# which clock port ??
@@ -17,4 +17,5 @@
set ::env(CLOCK_NET) "clk"
+set ::env(SYNTH_NO_FLAT) 1
set ::env(RUN_MAGIC) 1
diff --git a/openlane/input/config_spi.tcl b/openlane/input/striVe_spi/config.tcl
similarity index 64%
rename from openlane/input/config_spi.tcl
rename to openlane/input/striVe_spi/config.tcl
index 7dee8ac..779b128 100644
--- a/openlane/input/config_spi.tcl
+++ b/openlane/input/striVe_spi/config.tcl
@@ -1,7 +1,6 @@
set script_dir [file dirname [file normalize [info script]]]
set ::env(DESIGN_NAME) striVe_spi
-set ::env(VERILOG_FILES) "$script_dir/../../verilog/rtl/striVe_spi.v"
-set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+set ::env(VERILOG_FILES) "$script_dir/../../../verilog/rtl/striVe_spi.v"
set ::env(CLOCK_PERIOD) "10"
set ::env(CLOCK_PORT) "SCK"
diff --git a/verilog/rtl/striVe.v b/verilog/rtl/striVe.v
index b89a5eb..1fcd06c 100644
--- a/verilog/rtl/striVe.v
+++ b/verilog/rtl/striVe.v
@@ -35,12 +35,12 @@
// PDK IP
// Digital standard cells (to be changed to open-source library)
- `include "/ef/tech/SW/EFS8A/libs.ref/verilog/scs8hd/scs8hd.v"
+ // `include "/ef/tech/SW/EFS8A/libs.ref/verilog/scs8hd/scs8hd.v"
//`include "/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/scs8hd/verilog/scs8hd.v"
// I/O padframe cells
-`include "/ef/tech/SW/EFS8A/libs.ref/verilog/s8iom0s8/s8iom0s8.v"
-`include "/ef/tech/SW/EFS8A/libs.ref/verilog/s8iom0s8/power_pads_lib.v"
+`include "s8iom0s8.v"
+`include "power_pads_lib.v"
//`include "/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v"
//`include "/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v"
@@ -58,6 +58,10 @@
`include "striVe_clkrst.v"
`endif
+`ifdef PFG
+ `include "scs8hd_conb_1.v"
+`endif
+
`include "lvlshiftdown.v"
module striVe (vdd, vdd1v8, vss, gpio, xi, xo, adc0_in, adc1_in, adc_high, adc_low,
diff --git a/verilog/rtl/striVe_nopwr_nocorner.v b/verilog/rtl/striVe_nopwr_nocorner.v
new file mode 100644
index 0000000..4cbc8bc
--- /dev/null
+++ b/verilog/rtl/striVe_nopwr_nocorner.v
@@ -0,0 +1,1487 @@
+/*----------------------------------------------------------*/
+/* striVe, a raven/ravenna-like architecture in SkyWater s8 */
+/* */
+/* 1st edition, test of SkyWater s8 process */
+/* This version is missing all analog functionality, */
+/* including crystal oscillator, voltage regulator, and PLL */
+/* For simplicity, the pad arrangement of Raven has been */
+/* retained, even though many pads have no internal */
+/* connection. */
+/* */
+/* Copyright 2020 efabless, Inc. */
+/* Written by Tim Edwards, December 2019 */
+/* This file is open source hardware released under the */
+/* Apache 2.0 license. See file LICENSE. */
+/* */
+/*----------------------------------------------------------*/
+
+`timescale 1 ns / 1 ps
+
+/* Always define USE_PG_PIN (used by SkyWater cells) */
+/* But do not define SC_USE_PG_PIN */
+`define USE_PG_PIN
+
+/* Define LVS (equivalent to USE_PG_PIN, used by qflow) */
+/* `define LVS */
+
+/* Must define functional for now because otherwise the timing delays */
+/* are assumed, but they have been stripped out because some are not */
+/* parsed by iverilog. */
+
+`define functional
+
+// Define GL to use the gate-level netlists
+//`define GL
+
+// PDK IP
+// Digital standard cells (to be changed to open-source library)
+`ifdef NO_BLACKBOX
+`include "striVe_soc.v"
+`include "striVe_spi.v"
+`include "digital_pll.v"
+`include "striVe_clkrst.v"
+`include "lvlshiftdown.v"
+`include "scs8hd_conb_1.v"
+`endif
+
+// I/O padframe cells
+`include "../stubs/s8iom0s8.v"
+`include "../stubs/power_pads_lib.v"
+
+// Core cells, functional blackbox versions
+module striVe (vdd, vdd1v8, vss, gpio, xi, xo, adc0_in, adc1_in, adc_high, adc_low,
+ comp_inn, comp_inp, RSTB, ser_rx, ser_tx, irq, SDO, SDI, CSB, SCK,
+ xclk, flash_csb, flash_clk, flash_io0, flash_io1, flash_io2, flash_io3);
+ input vdd;
+ input vdd1v8;
+ input vss;
+ inout [15:0] gpio;
+ input xi; // CMOS clock input, not a crystal
+ output xo; // divide-by-16 clock output
+ input adc0_in;
+ input adc1_in;
+ input adc_high;
+ input adc_low;
+ input comp_inn;
+ input comp_inp;
+ input RSTB; // NOTE: Replaces analog_out pin from raven chip
+ input ser_rx;
+ output ser_tx;
+ input irq;
+ output SDO;
+ input SDI;
+ input CSB;
+ input SCK;
+ input xclk;
+ output flash_csb;
+ output flash_clk;
+ output flash_io0;
+ output flash_io1;
+ output flash_io2;
+ output flash_io3;
+
+ wire [15:0] gpio_out_core;
+ wire [15:0] gpio_in_core;
+ wire [15:0] gpio_mode0_core;
+ wire [15:0] gpio_mode1_core;
+ wire [15:0] gpio_outenb_core;
+ wire [15:0] gpio_inenb_core;
+
+ wire analog_a, analog_b; /* Placeholders for analog signals */
+
+ wire porb_h;
+ wire porb;
+ wire por_h;
+ wire por;
+ wire SCK_core;
+ wire SDI_core;
+ wire CSB_core;
+ wire SDO_core;
+ wire SDO_enb;
+ wire spi_ro_xtal_ena_core;
+ wire spi_ro_reg_ena_core;
+ wire spi_ro_pll_dco_ena_core;
+ wire [2:0] spi_ro_pll_sel_core;
+ wire [4:0] spi_ro_pll_div_core;
+ wire [25:0] spi_ro_pll_trim_core;
+ wire ext_clk_sel_core;
+ wire irq_spi_core;
+ wire ext_reset_core;
+ wire trap_core;
+ wire [11:0] spi_ro_mfgr_id_core;
+ wire [7:0] spi_ro_prod_id_core;
+ wire [3:0] spi_ro_mask_rev_core;
+/*
+ // Instantiate power cells for VDD3V3 domain (8 total; 4 high clamps and
+ // 4 low clamps)
+ s8iom0_vdda_hvc_pad vdd3v3hclamp [3:0] (
+ //.amuxbus_a(analog_a),
+ //.amuxbus_b(analog_b),
+ .drn_hvc(),
+ .src_bdy_hvc(),
+ //.vswitch(vdd),
+ //.vcchib(vdd1v8), // Hibernation supply
+ //.vccd(vdd1v8),
+ //.vdda(vdd), // Analog power supply
+ //.vssa(vss), // Analog ground
+ //.vddio(vdd), // Main (digital) power supply
+ //.vssio(vss), // Main (digital) ground
+ //.vssd(vss),
+ //.vddio_q(vdd), // (vdd low-noise) Tie to vddio if not using analog mux
+ //.vssio_q(vss) // (vss low-noise) Tie to vssio if not using analog mux
+ );
+
+ s8iom0_vdda_lvc_pad vdd3v3lclamp [3:0] (
+ //.amuxbus_a(analog_a),
+ //.amuxbus_b(analog_b),
+ .bdy2_b2b(),
+ .drn_lvc1(),
+ .drn_lvc2(),
+ .src_bdy_lvc1(),
+ .src_bdy_lvc2(),
+ //.vssa(vss),
+ //.vdda(vdd),
+ //.vswitch(vdd),
+ //.vddio_q(vdd),
+ //.vcchib(vdd1v8),
+ //.vddio(vdd),
+ //.vccd(vdd1v8),
+ //.vssio(vss),
+ //.vssd(vss),
+ //.vssio_q(vss)
+ );
+
+ // Instantiate the core voltage supply (since it is not generated on-chip)
+ // (1.8V) (4 total, 2 high and 2 low clamps)
+
+ s8iom0_vccd_hvc_pad vdd1v8hclamp [1:0] (
+ //.amuxbus_a(analog_a),
+ //.amuxbus_b(analog_b),
+ .drn_hvc(),
+ .src_bdy_hvc(),
+ //.vswitch(vdd),
+ //.vcchib(vdd1v8), // Hibernation supply
+ //.vccd(vdd1v8),
+ //.vdda(vdd), // Analog power supply
+ //.vssa(vss), // Analog ground
+ //.vddio(vdd), // Main (digital) power supply
+ //.vssio(vss), // Main (digital) ground
+ //.vssd(vss),
+ //.vddio_q(vdd), // (vdd low-noise) Tie to vddio if not using analog mux
+ //.vssio_q(vss) // (vss low-noise) Tie to vssio if not using analog mux
+ );
+
+ s8iom0_vccd_lvc_pad vdd1v8lclamp [1:0] (
+ //.amuxbus_a(analog_a),
+ //.amuxbus_b(analog_b),
+ .bdy2_b2b(),
+ .drn_lvc1(),
+ .drn_lvc2(),
+ .src_bdy_lvc1(),
+ .src_bdy_lvc2(),
+ //.vssa(vss),
+ //.vdda(vdd),
+ //.vswitch(vdd),
+ //.vddio_q(vdd),
+ //.vcchib(vdd1v8),
+ //.vddio(vdd),
+ //.vccd(vdd1v8),
+ //.vssio(vss),
+ //.vssd(vss),
+ //.vssio_q(vss)
+ );
+
+ // Instantiate ground cells (7 total, 4 high clamps and 3 low clamps)
+
+ s8iom0_vssa_hvc_pad vsshclamp [3:0] (
+ //.amuxbus_a(analog_a),
+ //.amuxbus_b(analog_b),
+ .drn_hvc(),
+ .src_bdy_hvc(),
+ //.vssa(vss),
+ //.vdda(vdd),
+ //.vswitch(vdd),
+ //.vddio_q(vdd),
+ //.vcchib(vdd1v8),
+ //.vddio(vdd),
+ //.vccd(vdd1v8),
+ //.vssio(vss),
+ //.vssd(vss),
+ //.vssio_q(vss)
+ );
+
+ s8iom0_vssa_lvc_pad vsslclamp [2:0] (
+ //.amuxbus_a(analog_a),
+ //.amuxbus_b(analog_b),
+ .bdy2_b2b(),
+ .drn_lvc1(),
+ .drn_lvc2(),
+ .src_bdy_lvc1(),
+ .src_bdy_lvc2(),
+ //.vssa(vss),
+ //.vdda(vdd),
+ //.vswitch(vdd),
+ //.vddio_q(vdd),
+ //.vcchib(vdd1v8), // Core voltage
+ //.vddio(vdd), // ESD power supply
+ //.vssio(vss), // ESD ground
+ //.vccd(vdd1v8),
+ //.vssio_q(vss)
+ );
+ */
+
+ // Instantiate GPIO v2 cell. These are used for both digital and analog
+ // functions, configured appropriately.
+ //
+ // GPIO pin description:
+ //
+ // general: signals with _h suffix are in the vddio (3.3V) domain. All
+ // other signals are in 1.8V domains (vccd or vcchib)
+
+ // out = Signal from core to pad (digital, 1.8V domain)
+ // oe_n = Output buffer enable (sense inverted)
+ // hld_h_n = Hold signals during deep sleep (sense inverted)
+ // enable_h = Power-on-reset (inverted)
+ // enable_inp_h = Defines state of input buffer output when disabled.
+ // Connect via loopback to tie_hi_esd or tie_lo_esd.
+ // enable_vdda_h = Power-on-reset (inverted) to analog section
+ // enable_vswitch_h = set to 0 if not using vswitch
+ // enable_vddio = set to 1 if vddio is up during deep sleep
+ // inp_dis = Disable input buffer
+ // ib_mode_sel = Input buffer mode select, 0 for 3.3V external signals, 1 for
+ // 1.8V external signals
+ // vtrip_se = Input buffer trip select, 0 for CMOS level, 1 for TTL level
+ // slow = 0 for fast slew, 1 for slow slew
+ // hld_ovr = override for pads that need to be enabled during deep sleep
+ // analog_en = enable analog functions
+ // analog_sel = select analog channel a or b
+ // analog_pol = analog select polarity
+ // dm = digital mode (3 bits) 000 = analog 001 = input only, 110 = output only
+ // vddio = Main 3.3V supply
+ // vddio_q = Quiet 3.3V supply
+ // vdda = Analog 3.3V supply
+ // vccd = Digital 1.8V supply
+ // vswitch = High-voltage supply for analog switches
+ // vcchib = Digital 1.8V supply live during deep sleep mode
+ // vssa = Analog ground
+ // vssd = Digital ground
+ // vssio_q = Quiet main ground
+ // vssio = Main ground
+ // pad = Signal on pad
+ // pad_a_noesd_h = Direct core connection to pad
+ // pad_a_esd_0_h = Core connection to pad through 150 ohms (primary)
+ // pad_a_esd_1_h = Core connection to pad through 150 ohms (secondary)
+ // amuxbus_a = Analog bus A
+ // amuxbus_b = Analog bus B
+ // in = Signal from pad to core (digital, 1.8V domain)
+ // in_h = Signal from pad to core (3.3V domain)
+ // tie_hi_esd = 3.3V output for loopback to enable_inp_h
+ // tie_lo_esd = ground output for loopback to enable_inp_h
+
+ // 37 instances: 16 general purpose digital, 2 for the crystal oscillator,
+ // 4 for the ADC, 1 for the analog out, 2 for the comparator inputs,
+ // one for the IRQ input, one for the xclk input, 6 for the SPI flash
+ // signals, and 4 for the housekeeping SPI signals.
+
+ // NOTE: To pass a vector to array dm in an array of instances gpio_pad,
+ // the array needs to be rearranged. Reconstruct the needed 48-bit vector
+ // (3 bit signal * 16 instances).
+ //
+ // Also note: Preferable to use a generate block, but that is incompatible
+ // with the current version of padframe_generator. . .
+
+ wire [47:0] dm_all;
+
+ assign dm_all = {gpio_mode1_core[15], gpio_mode1_core[15], gpio_mode0_core[15],
+ gpio_mode1_core[14], gpio_mode1_core[14], gpio_mode0_core[14],
+ gpio_mode1_core[13], gpio_mode1_core[13], gpio_mode0_core[13],
+ gpio_mode1_core[12], gpio_mode1_core[12], gpio_mode0_core[12],
+ gpio_mode1_core[11], gpio_mode1_core[11], gpio_mode0_core[11],
+ gpio_mode1_core[10], gpio_mode1_core[10], gpio_mode0_core[10],
+ gpio_mode1_core[9], gpio_mode1_core[9], gpio_mode0_core[9],
+ gpio_mode1_core[8], gpio_mode1_core[8], gpio_mode0_core[8],
+ gpio_mode1_core[7], gpio_mode1_core[7], gpio_mode0_core[7],
+ gpio_mode1_core[6], gpio_mode1_core[6], gpio_mode0_core[6],
+ gpio_mode1_core[5], gpio_mode1_core[5], gpio_mode0_core[5],
+ gpio_mode1_core[4], gpio_mode1_core[4], gpio_mode0_core[4],
+ gpio_mode1_core[3], gpio_mode1_core[3], gpio_mode0_core[3],
+ gpio_mode1_core[2], gpio_mode1_core[2], gpio_mode0_core[2],
+ gpio_mode1_core[1], gpio_mode1_core[1], gpio_mode0_core[1],
+ gpio_mode1_core[0], gpio_mode1_core[0], gpio_mode0_core[0]};
+
+ // GPIO pads
+ s8iom0_gpiov2_pad gpio_pad [15:0] (
+ .out(gpio_out_core), // Signal from core to pad
+ .oe_n(gpio_outenb_core), // Output enable (sense inverted)
+ .hld_h_n(vdd), // Hold signals during deep sleep (sense inverted)
+ .enable_h(porb_h), // Post-reset enable
+ .enable_inp_h(loopb0), // Input buffer state when disabled
+ .enable_vdda_h(porb_h), //
+ .enable_vswitch_h(vss), //
+ .enable_vddio(vdd1v8), //
+ .inp_dis(gpio_inenb_core), // Disable input buffer
+ .ib_mode_sel(vss), //
+ .vtrip_sel(vss), //
+ .slow(vss), //
+ .hld_ovr(vss), //
+ .analog_en(vss), //
+ .analog_sel(vss), //
+ .analog_pol(vss), //
+ .dm(dm_all), // (3 bits) Mode control
+ //.vddio(vdd),
+ //.vddio_q(vdd),
+ //.vdda(vdd),
+ //.vccd(vdd1v8),
+ //.vswitch(vdd),
+ //.vcchib(vdd1v8),
+ //.vssa(vss),
+ //.vssd(vss),
+ //.vssio_q(vss),
+ //.vssio(vss),
+ //.pad(gpio),
+ .pad_a_noesd_h(), // Direct pad connection
+ .pad_a_esd_0_h(), // Pad connection through 150 ohms
+ .pad_a_esd_1_h(), // Pad connection through 150 ohms
+ //.amuxbus_a(analog_a),
+ //.amuxbus_b(analog_b),
+ .in(gpio_in_core), // Signal from pad to core
+ .in_h(), // VDDA domain signal (unused)
+ .tie_hi_esd(),
+ .tie_lo_esd(loopb0)
+ );
+
+ s8iom0_gpiov2_pad xi_pad (
+ .out(), // Signal from core to pad
+ .oe_n(vdd1v8), // Output enable (sense inverted)
+ .hld_h_n(vdd), // Hold
+ .enable_h(porb_h), // Enable
+ .enable_inp_h(loopb1), // Enable input buffer
+ .enable_vdda_h(porb_h), //
+ .enable_vswitch_h(vss), //
+ .enable_vddio(vdd1v8), //
+ .inp_dis(por), // Disable input buffer
+ .ib_mode_sel(vss), //
+ .vtrip_sel(vss), //
+ .slow(vss), //
+ .hld_ovr(vss), //
+ .analog_en(vss), //
+ .analog_sel(vss), //
+ .analog_pol(vss), //
+ .dm({vss, vss, vdd1v8}), // (3 bits) Mode control
+ //.vddio(vdd),
+ //.vddio_q(vdd),
+ //.vdda(vdd),
+ //.vccd(vdd1v8),
+ //.vswitch(vdd),
+ //.vcchib(vdd1v8),
+ //.vssa(vss),
+ //.vssd(vss),
+ //.vssio_q(vss),
+ //.vssio(vss),
+ //.pad(xi),
+ .pad_a_noesd_h(), // Direct pad connection
+ .pad_a_esd_0_h(), // Pad connection through 150 ohms
+ .pad_a_esd_1_h(), // Pad connection through 150 ohms
+ //.amuxbus_a(analog_a),
+ //.amuxbus_b(analog_b),
+ .in(xi_core), // Signal from pad to core
+ .in_h(),
+ .tie_hi_esd(),
+ .tie_lo_esd(loopb1)
+ );
+
+ s8iom0_gpiov2_pad xo_pad (
+ .out(pll_clk16), // Signal from core to pad
+ .oe_n(vss), // Output enable (sense inverted)
+ .hld_h_n(vdd), // Hold
+ .enable_h(porb_h), // Enable
+ .enable_inp_h(loopb2), // Enable input buffer
+ .enable_vdda_h(porb_h), //
+ .enable_vswitch_h(vss), //
+ .enable_vddio(vdd1v8), //
+ .inp_dis(vdd1v8), // Disable input buffer
+ .ib_mode_sel(vss), //
+ .vtrip_sel(vss), //
+ .slow(vss), //
+ .hld_ovr(vss), //
+ .analog_en(vss), //
+ .analog_sel(vss), //
+ .analog_pol(vss), //
+ .dm({vdd1v8, vdd1v8, vss}), // (3 bits) Mode control
+ //.vddio(vdd),
+ //.vddio_q(vdd),
+ //.vdda(vdd),
+ //.vccd(vdd1v8),
+ //.vswitch(vdd),
+ //.vcchib(vdd1v8),
+ //.vssa(vss),
+ //.vssd(vss),
+ //.vssio_q(vss),
+ //.vssio(vss),
+ //.pad(xo),
+ .pad_a_noesd_h(), // Direct pad connection
+ .pad_a_esd_0_h(), // Pad connection through 150 ohms
+ .pad_a_esd_1_h(), // Pad connection through 150 ohms
+ //.amuxbus_a(analog_a),
+ //.amuxbus_b(analog_b),
+ .in(), // Signal from pad to core
+ .in_h(),
+ .tie_hi_esd(),
+ .tie_lo_esd(loopb2)
+ );
+
+ s8iom0_gpiov2_pad adc0_in_pad (
+ .out(vss), // Signal from core to pad
+ .oe_n(vdd1v8), // Output enable (sense inverted)
+ .hld_h_n(vdd), // Hold
+ .enable_h(porb_h), // Enable
+ .enable_inp_h(loopb3), // Enable input buffer
+ .enable_vdda_h(porb_h), //
+ .enable_vswitch_h(vss), //
+ .enable_vddio(vdd1v8), //
+ .inp_dis(vdd1v8), // Disable input buffer
+ .ib_mode_sel(vss), //
+ .vtrip_sel(vss), //
+ .slow(vss), //
+ .hld_ovr(vss), //
+ .analog_en(vdd1v8), //
+ .analog_sel(vss), //
+ .analog_pol(vss), //
+ .dm({vss, vss, vss}), // (3 bits) Mode control
+ //.vddio(vdd),
+ //.vddio_q(vdd),
+ //.vdda(vdd),
+ //.vccd(vdd1v8),
+ //.vswitch(vdd),
+ //.vcchib(vdd1v8),
+ //.vssa(vss),
+ //.vssd(vss),
+ //.vssio_q(vss),
+ //.vssio(vss),
+ //.pad(adc0_in),
+ .pad_a_noesd_h(), // Direct pad connection
+ .pad_a_esd_0_h(), // Pad connection through 150 ohms
+ .pad_a_esd_1_h(), // Pad connection through 150 ohms
+ //.amuxbus_a(analog_a),
+ //.amuxbus_b(analog_b),
+ .in(), // Signal from pad to core
+ .in_h(),
+ .tie_hi_esd(),
+ .tie_lo_esd()
+ );
+
+ s8iom0_gpiov2_pad adc1_in_pad (
+ .out(vss), // Signal from core to pad
+ .oe_n(vdd1v8), // Output enable (sense inverted)
+ .hld_h_n(vdd), // Hold
+ .enable_h(porb_h), // Enable
+ .enable_inp_h(loopb4), // Enable input buffer
+ .enable_vdda_h(porb_h), //
+ .enable_vswitch_h(vss), //
+ .enable_vddio(vdd1v8), //
+ .inp_dis(vdd1v8), // Disable input buffer
+ .ib_mode_sel(vss), //
+ .vtrip_sel(vss), //
+ .slow(vss), //
+ .hld_ovr(vss), //
+ .analog_en(vdd1v8), //
+ .analog_sel(vss), //
+ .analog_pol(vss), //
+ .dm({vss, vss, vss}), // (3 bits) Mode control
+ //.vddio(vdd),
+ //.vddio_q(vdd),
+ //.vdda(vdd),
+ //.vccd(vdd1v8),
+ //.vswitch(vdd),
+ //.vcchib(vdd1v8),
+ //.vssa(vss),
+ //.vssd(vss),
+ //.vssio_q(vss),
+ //.vssio(vss),
+ //.pad(adc1_in),
+ .pad_a_noesd_h(), // Direct pad connection
+ .pad_a_esd_0_h(), // Pad connection through 150 ohms
+ .pad_a_esd_1_h(), // Pad connection through 150 ohms
+ //.amuxbus_a(analog_a),
+ //.amuxbus_b(analog_b),
+ .in(), // Signal from pad to core
+ .in_h(),
+ .tie_hi_esd(),
+ .tie_lo_esd()
+ );
+
+ s8iom0_gpiov2_pad adc_high_pad (
+ .out(vss), // Signal from core to pad
+ .oe_n(vdd1v8), // Output enable (sense inverted)
+ .hld_h_n(vdd), // Hold
+ .enable_h(porb_h), // Enable
+ .enable_inp_h(loopb5), // Enable input buffer
+ .enable_vdda_h(porb_h), //
+ .enable_vswitch_h(vss), //
+ .enable_vddio(vdd1v8), //
+ .inp_dis(vdd1v8), // Disable input buffer
+ .ib_mode_sel(vss), //
+ .vtrip_sel(vss), //
+ .slow(vss), //
+ .hld_ovr(vss), //
+ .analog_en(vdd1v8), //
+ .analog_sel(vdd1v8), //
+ .analog_pol(vdd1v8), //
+ .dm({vss, vss, vss}), // (3 bits) Mode control
+ //.vddio(vdd),
+ //.vddio_q(vdd),
+ //.vdda(vdd),
+ //.vccd(vdd1v8),
+ //.vswitch(vdd),
+ //.vcchib(vdd1v8),
+ //.vssa(vss),
+ //.vssd(vss),
+ //.vssio_q(vss),
+ //.vssio(vss),
+ //.pad(adc_high),
+ .pad_a_noesd_h(), // Direct pad connection
+ .pad_a_esd_0_h(), // Pad connection through 150 ohms
+ .pad_a_esd_1_h(), // Pad connection through 150 ohms
+ //.amuxbus_a(analog_a),
+ //.amuxbus_b(analog_b),
+ .in(), // Signal from pad to core
+ .in_h(),
+ .tie_hi_esd(),
+ .tie_lo_esd()
+ );
+
+ s8iom0_gpiov2_pad adc_low_pad (
+ .out(vss), // Signal from core to pad
+ .oe_n(vdd1v8), // Output enable (sense inverted)
+ .hld_h_n(vdd), // Hold
+ .enable_h(porb_h), // Enable
+ .enable_inp_h(loopb6), // Enable input buffer
+ .enable_vdda_h(porb_h), //
+ .enable_vswitch_h(vss), //
+ .enable_vddio(vdd1v8), //
+ .inp_dis(vdd1v8), // Disable input buffer
+ .ib_mode_sel(vss), //
+ .vtrip_sel(vss), //
+ .slow(vss), //
+ .hld_ovr(vss), //
+ .analog_en(vdd1v8), //
+ .analog_sel(vss), //
+ .analog_pol(vss), //
+ .dm({vss, vss, vss}), // (3 bits) Mode control
+ //.vddio(vdd),
+ //.vddio_q(vdd),
+ //.vdda(vdd),
+ //.vccd(vdd1v8),
+ //.vswitch(vdd),
+ //.vcchib(vdd1v8),
+ //.vssa(vss),
+ //.vssd(vss),
+ //.vssio_q(vss),
+ //.vssio(vss),
+ //.pad(adc_low),
+ .pad_a_noesd_h(), // Direct pad connection
+ .pad_a_esd_0_h(), // Pad connection through 150 ohms
+ .pad_a_esd_1_h(), // Pad connection through 150 ohms
+ //.amuxbus_a(analog_a),
+ //.amuxbus_b(analog_b),
+ .in(), // Signal from pad to core
+ .in_h(),
+ .tie_hi_esd(),
+ .tie_lo_esd()
+ );
+
+ s8iom0_gpiov2_pad comp_inn_pad (
+ .out(vss), // Signal from core to pad
+ .oe_n(vdd1v8), // Output enable (sense inverted)
+ .hld_h_n(vdd), // Hold
+ .enable_h(porb_h), // Enable
+ .enable_inp_h(loopb7), // Enable input buffer
+ .enable_vdda_h(porb_h), //
+ .enable_vswitch_h(vss), //
+ .enable_vddio(vdd1v8), //
+ .inp_dis(vdd1v8), // Disable input buffer
+ .ib_mode_sel(vss), //
+ .vtrip_sel(vss), //
+ .slow(vss), //
+ .hld_ovr(vss), //
+ .analog_en(vdd1v8), //
+ .analog_sel(vss), //
+ .analog_pol(vss), //
+ .dm({vss, vss, vss}), // (3 bits) Mode control
+ //.vddio(vdd),
+ //.vddio_q(vdd),
+ //.vdda(vdd),
+ //.vccd(vdd1v8),
+ //.vswitch(vdd),
+ //.vcchib(vdd1v8),
+ //.vssa(vss),
+ //.vssd(vss),
+ //.vssio_q(vss),
+ //.vssio(vss),
+ //.pad(comp_inn),
+ .pad_a_noesd_h(), // Direct pad connection
+ .pad_a_esd_0_h(), // Pad connection through 150 ohms
+ .pad_a_esd_1_h(), // Pad connection through 150 ohms
+ //.amuxbus_a(analog_a),
+ //.amuxbus_b(analog_b),
+ .in(), // Signal from pad to core
+ .in_h(),
+ .tie_hi_esd(),
+ .tie_lo_esd()
+ );
+
+ s8iom0_gpiov2_pad comp_inp_pad (
+ .out(vss), // Signal from core to pad
+ .oe_n(vdd1v8), // Output enable (sense inverted)
+ .hld_h_n(vdd), // Hold
+ .enable_h(porb_h), // Enable
+ .enable_inp_h(loopb8), // Enable input buffer
+ .enable_vdda_h(porb_h), //
+ .enable_vswitch_h(vss), //
+ .enable_vddio(vdd1v8), //
+ .inp_dis(vdd1v8), // Disable input buffer
+ .ib_mode_sel(vss), //
+ .vtrip_sel(vss), //
+ .slow(vss), //
+ .hld_ovr(vss), //
+ .analog_en(vdd1v8), //
+ .analog_sel(vdd1v8), //
+ .analog_pol(vss), //
+ .dm({vss, vss, vss}), // (3 bits) Mode control
+ //.vddio(vdd),
+ //.vddio_q(vdd),
+ //.vdda(vdd),
+ //.vccd(vdd1v8),
+ //.vswitch(vdd),
+ //.vcchib(vdd1v8),
+ //.vssa(vss),
+ //.vssd(vss),
+ //.vssio_q(vss),
+ //.vssio(vss),
+ //.pad(comp_inp),
+ .pad_a_noesd_h(), // Direct pad connection
+ .pad_a_esd_0_h(), // Pad connection through 150 ohms
+ .pad_a_esd_1_h(), // Pad connection through 150 ohms
+ //.amuxbus_a(analog_a),
+ //.amuxbus_b(analog_b),
+ .in(), // Signal from pad to core
+ .in_h(),
+ .tie_hi_esd(),
+ .tie_lo_esd()
+ );
+
+ // NOTE: The analog_out pad from the raven chip has been replaced by
+ // the digital reset input RSTB on striVe due to the lack of an on-board
+ // power-on-reset circuit. The XRES pad is used for providing a glitch-
+ // free reset.
+
+ s8iom0s8_top_xres4v2 RSTB_pad (
+ //.pad(RSTB),
+
+ .tie_weak_hi_h(xresloop), // Loop-back connection to pad through pad_a_esd_h
+ .tie_hi_esd(),
+ .tie_lo_esd(),
+ .pad_a_esd_h(xresloop),
+ .xres_h_n(porb_h),
+ .disable_pullup_h(vss), // 0 = enable pull-up on reset pad
+ .enable_h(vdd), // Power-on-reset to the power-on-reset input??
+ .en_vddio_sig_h(vss), // No idea.
+ .inp_sel_h(vss), // 1 = use filt_in_h else filter the pad input
+ .filt_in_h(vss), // Alternate input for glitch filter
+ .pullup_h(vss), // Pullup connection for alternate filter input
+ .enable_vddio(vdd1v8),
+ //.vssio(vss),
+ //.vddio(vdd),
+ //.vddio_q(vdd),
+ //.vssio_q(vss),
+ //.amuxbus_a(analog_a),
+ //.amuxbus_b(analog_b),
+ //.vssd(vss),
+ //.vssa(vss),
+ //.vswitch(vdd),
+ //.vdda(vdd),
+ //.vccd(vdd1v8),
+ //.vcchib(vdd1v8)
+ );
+
+ s8iom0_gpiov2_pad irq_pad (
+ .out(vss), // Signal from core to pad
+ .oe_n(vdd1v8), // Output enable (sense inverted)
+ .hld_h_n(vdd), // Hold
+ .enable_h(porb_h), // Enable
+ .enable_inp_h(loopb10), // Enable input buffer
+ .enable_vdda_h(porb_h), //
+ .enable_vswitch_h(vss), //
+ .enable_vddio(vdd1v8), //
+ .inp_dis(por), // Disable input buffer
+ .ib_mode_sel(vss), //
+ .vtrip_sel(vss), //
+ .slow(vss), //
+ .hld_ovr(vss), //
+ .analog_en(vss), //
+ .analog_sel(vss), //
+ .analog_pol(vss), //
+ .dm({vss, vss, vdd1v8}), // (3 bits) Mode control
+ //.vddio(vdd),
+ //.vddio_q(vdd),
+ //.vdda(vdd),
+ //.vccd(vdd1v8),
+ //.vswitch(vdd),
+ //.vcchib(vdd1v8),
+ //.vssa(vss),
+ //.vssd(vss),
+ //.vssio_q(vss),
+ //.vssio(vss),
+ //.pad(irq),
+ .pad_a_noesd_h(), // Direct pad connection
+ .pad_a_esd_0_h(), // Pad connection through 150 ohms
+ .pad_a_esd_1_h(), // Pad connection through 150 ohms
+ //.amuxbus_a(analog_a),
+ //.amuxbus_b(analog_b),
+ .in(irq_pin_core), // Signal from pad to core
+ .in_h(),
+ .tie_hi_esd(),
+ .tie_lo_esd(loopb10)
+ );
+
+ s8iom0_gpiov2_pad SDO_pad (
+ .out(SDO_core), // Signal from core to pad
+ .oe_n(SDO_enb), // Output enable (sense inverted)
+ .hld_h_n(vdd), // Hold
+ .enable_h(porb_h), // Enable
+ .enable_inp_h(loopb11), // Enable input buffer
+ .enable_vdda_h(porb_h), //
+ .enable_vswitch_h(vss), //
+ .enable_vddio(vdd1v8), //
+ .inp_dis(vdd1v8), // Disable input buffer
+ .ib_mode_sel(vss), //
+ .vtrip_sel(vss), //
+ .slow(vss), //
+ .hld_ovr(vss), //
+ .analog_en(vss), //
+ .analog_sel(vss), //
+ .analog_pol(vss), //
+ .dm({vdd1v8, vdd1v8, vss}), // (3 bits) Mode control
+ //.vddio(vdd),
+ //.vddio_q(vdd),
+ //.vdda(vdd),
+ //.vccd(vdd1v8),
+ //.vswitch(vdd),
+ //.vcchib(vdd1v8),
+ //.vssa(vss),
+ //.vssd(vss),
+ //.vssio_q(vss),
+ //.vssio(vss),
+ //.pad(SDO),
+ .pad_a_noesd_h(), // Direct pad connection
+ .pad_a_esd_0_h(), // Pad connection through 150 ohms
+ .pad_a_esd_1_h(), // Pad connection through 150 ohms
+ //.amuxbus_a(analog_a),
+ //.amuxbus_b(analog_b),
+ .in(), // Signal from pad to core
+ .in_h(),
+ .tie_hi_esd(),
+ .tie_lo_esd(loopb11)
+ );
+
+ s8iom0_gpiov2_pad SDI_pad (
+ .out(vss), // Signal from core to pad
+ .oe_n(vdd1v8), // Output enable (sense inverted)
+ .hld_h_n(vdd), // Hold
+ .enable_h(porb_h), // Enable
+ .enable_inp_h(loopb12), // Enable input buffer
+ .enable_vdda_h(porb_h), //
+ .enable_vswitch_h(vss), //
+ .enable_vddio(vdd1v8), //
+ .inp_dis(por), // Disable input buffer
+ .ib_mode_sel(vss), //
+ .vtrip_sel(vss), //
+ .slow(vss), //
+ .hld_ovr(vss), //
+ .analog_en(vss), //
+ .analog_sel(vss), //
+ .analog_pol(vss), //
+ .dm({vss, vss, vdd1v8}), // (3 bits) Mode control
+ //.vddio(vdd),
+ //.vddio_q(vdd),
+ //.vdda(vdd),
+ //.vccd(vdd1v8),
+ //.vswitch(vdd),
+ //.vcchib(vdd1v8),
+ //.vssa(vss),
+ //.vssd(vss),
+ //.vssio_q(vss),
+ //.vssio(vss),
+ //.pad(SDI),
+ .pad_a_noesd_h(), // Direct pad connection
+ .pad_a_esd_0_h(), // Pad connection through 150 ohms
+ .pad_a_esd_1_h(), // Pad connection through 150 ohms
+ //.amuxbus_a(analog_a),
+ //.amuxbus_b(analog_b),
+ .in(SDI_core), // Signal from pad to core
+ .in_h(SDI_core_h),
+ .tie_hi_esd(),
+ .tie_lo_esd()
+ );
+
+ s8iom0_gpiov2_pad CSB_pad (
+ .out(vss), // Signal from core to pad
+ .oe_n(vdd1v8), // Output enable (sense inverted)
+ .hld_h_n(vdd), // Hold
+ .enable_h(porb_h), // Enable
+ .enable_inp_h(loopb13), // Enable input buffer
+ .enable_vdda_h(porb_h), //
+ .enable_vswitch_h(vss), //
+ .enable_vddio(vdd1v8), //
+ .inp_dis(por), // Disable input buffer
+ .ib_mode_sel(vss), //
+ .vtrip_sel(vss), //
+ .slow(vss), //
+ .hld_ovr(vss), //
+ .analog_en(vss), //
+ .analog_sel(vss), //
+ .analog_pol(vss), //
+ .dm({vss, vss, vdd1v8}), // (3 bits) Mode control
+ //.vddio(vdd),
+ //.vddio_q(vdd),
+ //.vdda(vdd),
+ //.vccd(vdd1v8),
+ //.vswitch(vdd),
+ //.vcchib(vdd1v8),
+ //.vssa(vss),
+ //.vssd(vss),
+ //.vssio_q(vss),
+ //.vssio(vss),
+ //.pad(CSB),
+ .pad_a_noesd_h(), // Direct pad connection
+ .pad_a_esd_0_h(), // Pad connection through 150 ohms
+ .pad_a_esd_1_h(), // Pad connection through 150 ohms
+ //.amuxbus_a(analog_a),
+ //.amuxbus_b(analog_b),
+ .in(CSB_core), // Signal from pad to core
+ .in_h(CSB_core_h),
+ .tie_hi_esd(),
+ .tie_lo_esd(loopb13)
+ );
+
+ s8iom0_gpiov2_pad SCK_pad (
+ .out(vss), // Signal from core to pad
+ .oe_n(vdd1v8), // Output enable (sense inverted)
+ .hld_h_n(vdd), // Hold
+ .enable_h(porb_h), // Enable
+ .enable_inp_h(loopb14), // Enable input buffer
+ .enable_vdda_h(porb_h), //
+ .enable_vswitch_h(vss), //
+ .enable_vddio(vdd1v8), //
+ .inp_dis(por), // Disable input buffer
+ .ib_mode_sel(vss), //
+ .vtrip_sel(vss), //
+ .slow(vss), //
+ .hld_ovr(vss), //
+ .analog_en(vss), //
+ .analog_sel(vss), //
+ .analog_pol(vss), //
+ .dm({vss, vss, vdd1v8}), // (3 bits) Mode control
+ //.vddio(vdd),
+ //.vddio_q(vdd),
+ //.vdda(vdd),
+ //.vccd(vdd1v8),
+ //.vswitch(vdd),
+ //.vcchib(vdd1v8),
+ //.vssa(vss),
+ //.vssd(vss),
+ //.vssio_q(vss),
+ //.vssio(vss),
+ //.pad(SCK),
+ .pad_a_noesd_h(), // Direct pad connection
+ .pad_a_esd_0_h(), // Pad connection through 150 ohms
+ .pad_a_esd_1_h(), // Pad connection through 150 ohms
+ //.amuxbus_a(analog_a),
+ //.amuxbus_b(analog_b),
+ .in(SCK_core), // Signal from pad to core
+ .in_h(SCK_core_h), // Signal in vdda domain (3.3V)
+ .tie_hi_esd(),
+ .tie_lo_esd(loopb14)
+ );
+
+ s8iom0_gpiov2_pad xclk_pad (
+ .out(vss), // Signal from core to pad
+ .oe_n(vdd1v8), // Output enable (sense inverted)
+ .hld_h_n(vdd), // Hold
+ .enable_h(porb_h), // Enable
+ .enable_inp_h(loopb15), // Enable input buffer
+ .enable_vdda_h(porb_h), //
+ .enable_vswitch_h(vss), //
+ .enable_vddio(vdd1v8), //
+ .inp_dis(por), // Disable input buffer
+ .ib_mode_sel(vss), //
+ .vtrip_sel(vss), //
+ .slow(vss), //
+ .hld_ovr(vss), //
+ .analog_en(vss), //
+ .analog_sel(vss), //
+ .analog_pol(vss), //
+ .dm({vss, vss, vdd1v8}), // (3 bits) Mode control
+ //.vddio(vdd),
+ //.vddio_q(vdd),
+ //.vdda(vdd),
+ //.vccd(vdd1v8),
+ //.vswitch(vdd),
+ //.vcchib(vdd1v8),
+ //.vssa(vss),
+ //.vssd(vss),
+ //.vssio_q(vss),
+ //.vssio(vss),
+ //.pad(xclk),
+ .pad_a_noesd_h(), // Direct pad connection
+ .pad_a_esd_0_h(), // Pad connection through 150 ohms
+ .pad_a_esd_1_h(), // Pad connection through 150 ohms
+ //.amuxbus_a(analog_a),
+ //.amuxbus_b(analog_b),
+ .in(ext_clk_core), // Signal from pad to core
+ .in_h(),
+ .tie_hi_esd(),
+ .tie_lo_esd(loopb15)
+ );
+
+ s8iom0_gpiov2_pad flash_csb_pad (
+ .out(flash_csb_core), // Signal from core to pad
+ .oe_n(vss), // Output enable (sense inverted)
+ .hld_h_n(vdd), // Hold
+ .enable_h(porb_h), // Enable
+ .enable_inp_h(loopb16), // Enable input buffer
+ .enable_vdda_h(porb_h), //
+ .enable_vswitch_h(vss), //
+ .enable_vddio(vdd1v8), //
+ .inp_dis(vdd1v8), // Disable input buffer
+ .ib_mode_sel(vss), //
+ .vtrip_sel(vss), //
+ .slow(vss), //
+ .hld_ovr(vss), //
+ .analog_en(vss), //
+ .analog_sel(vss), //
+ .analog_pol(vss), //
+ .dm({vdd1v8, vdd1v8, vss}), // (3 bits) Mode control
+ //.vddio(vdd),
+ //.vddio_q(vdd),
+ //.vdda(vdd),
+ //.vccd(vdd1v8),
+ //.vswitch(vdd),
+ //.vcchib(vdd1v8),
+ //.vssa(vss),
+ //.vssd(vss),
+ //.vssio_q(vss),
+ //.vssio(vss),
+ //.pad(flash_csb),
+ .pad_a_noesd_h(), // Direct pad connection
+ .pad_a_esd_0_h(), // Pad connection through 150 ohms
+ .pad_a_esd_1_h(), // Pad connection through 150 ohms
+ //.amuxbus_a(analog_a),
+ //.amuxbus_b(analog_b),
+ .in(), // Signal from pad to core
+ .in_h(),
+ .tie_hi_esd(),
+ .tie_lo_esd()
+ );
+
+ s8iom0_gpiov2_pad flash_clk_pad (
+ .out(flash_clk_core), // Signal from core to pad
+ .oe_n(vss), // Output enable (sense inverted)
+ .hld_h_n(vdd), // Hold
+ .enable_h(porb_h), // Enable
+ .enable_inp_h(loopb17), // Enable input buffer
+ .enable_vdda_h(porb_h), //
+ .enable_vswitch_h(vss), //
+ .enable_vddio(vdd1v8), //
+ .inp_dis(vdd1v8), // Disable input buffer
+ .ib_mode_sel(vss), //
+ .vtrip_sel(vss), //
+ .slow(vss), //
+ .hld_ovr(vss), //
+ .analog_en(vss), //
+ .analog_sel(vss), //
+ .analog_pol(vss), //
+ .dm({vdd1v8, vdd1v8, vss}), // (3 bits) Mode control
+ //.vddio(vdd),
+ //.vddio_q(vdd),
+ //.vdda(vdd),
+ //.vccd(vdd1v8),
+ //.vswitch(vdd),
+ //.vcchib(vdd1v8),
+ //.vssa(vss),
+ //.vssd(vss),
+ //.vssio_q(vss),
+ //.vssio(vss),
+ //.pad(flash_clk),
+ .pad_a_noesd_h(), // Direct pad connection
+ .pad_a_esd_0_h(), // Pad connection through 150 ohms
+ .pad_a_esd_1_h(), // Pad connection through 150 ohms
+ //.amuxbus_a(analog_a),
+ //.amuxbus_b(analog_b),
+ .in(), // Signal from pad to core
+ .in_h(),
+ .tie_hi_esd(),
+ .tie_lo_esd()
+ );
+
+ s8iom0_gpiov2_pad flash_io0_pad (
+ .out(flash_io0_do_core), // Signal from core to pad
+ .oe_n(flash_io0_oeb_core), // Output enable (sense inverted)
+ .hld_h_n(vdd), // Hold
+ .enable_h(porb_h), // Enable
+ .enable_inp_h(loopb18), // Enable input buffer
+ .enable_vdda_h(porb_h), //
+ .enable_vswitch_h(vss), //
+ .enable_vddio(vdd1v8), //
+ .inp_dis(flash_io0_ieb_core), // Disable input buffer
+ .ib_mode_sel(vss), //
+ .vtrip_sel(vss), //
+ .slow(vss), //
+ .hld_ovr(vss), //
+ .analog_en(vss), //
+ .analog_sel(vss), //
+ .analog_pol(vss), //
+ .dm({flash_io0_ieb_core, flash_io0_ieb_core, flash_io0_oeb_core}), // (3 bits) Mode control
+ //.vddio(vdd),
+ //.vddio_q(vdd),
+ //.vdda(vdd),
+ //.vccd(vdd1v8),
+ //.vswitch(vdd),
+ //.vcchib(vdd1v8),
+ //.vssa(vss),
+ //.vssd(vss),
+ //.vssio_q(vss),
+ //.vssio(vss),
+ //.pad(flash_io0),
+ .pad_a_noesd_h(), // Direct pad connection
+ .pad_a_esd_0_h(), // Pad connection through 150 ohms
+ .pad_a_esd_1_h(), // Pad connection through 150 ohms
+ //.amuxbus_a(analog_a),
+ //.amuxbus_b(analog_b),
+ .in(flash_io0_di_core), // Signal from pad to core
+ .in_h(),
+ .tie_hi_esd(),
+ .tie_lo_esd(loopb18)
+ );
+
+ s8iom0_gpiov2_pad flash_io1_pad (
+ .out(flash_io1_do_core), // Signal from core to pad
+ .oe_n(flash_io1_oeb_core), // Output enable (sense inverted)
+ .hld_h_n(vdd), // Hold
+ .enable_h(porb_h), // Enable
+ .enable_inp_h(loopb19), // Enable input buffer
+ .enable_vdda_h(porb_h), //
+ .enable_vswitch_h(vss), //
+ .enable_vddio(vdd1v8), //
+ .inp_dis(flash_io1_ieb_core), // Disable input buffer
+ .ib_mode_sel(vss), //
+ .vtrip_sel(vss), //
+ .slow(vss), //
+ .hld_ovr(vss), //
+ .analog_en(vss), //
+ .analog_sel(vss), //
+ .analog_pol(vss), //
+ .dm({flash_io1_ieb_core, flash_io1_ieb_core, flash_io1_oeb_core}), // (3 bits) Mode control
+ //.vddio(vdd),
+ //.vddio_q(vdd),
+ //.vdda(vdd),
+ //.vccd(vdd1v8),
+ //.vswitch(vdd),
+ //.vcchib(vdd1v8),
+ //.vssa(vss),
+ //.vssd(vss),
+ //.vssio_q(vss),
+ //.vssio(vss),
+ //.pad(flash_io1),
+ .pad_a_noesd_h(), // Direct pad connection
+ .pad_a_esd_0_h(), // Pad connection through 150 ohms
+ .pad_a_esd_1_h(), // Pad connection through 150 ohms
+ //.amuxbus_a(analog_a),
+ //.amuxbus_b(analog_b),
+ .in(flash_io1_di_core), // Signal from pad to core
+ .in_h(),
+ .tie_hi_esd(),
+ .tie_lo_esd(loopb19)
+ );
+
+ s8iom0_gpiov2_pad flash_io2_pad (
+ .out(flash_io2_do_core), // Signal from core to pad
+ .oe_n(flash_io2_oeb_core), // Output enable (sense inverted)
+ .hld_h_n(vdd), // Hold
+ .enable_h(porb_h), // Enable
+ .enable_inp_h(loopb20), // Enable input buffer
+ .enable_vdda_h(porb_h), //
+ .enable_vswitch_h(vss), //
+ .enable_vddio(vdd1v8), //
+ .inp_dis(flash_io2_ieb_core), // Disable input buffer
+ .ib_mode_sel(vss), //
+ .vtrip_sel(vss), //
+ .slow(vss), //
+ .hld_ovr(vss), //
+ .analog_en(vss), //
+ .analog_sel(vss), //
+ .analog_pol(vss), //
+ .dm({flash_io2_ieb_core, flash_io2_ieb_core, flash_io2_oeb_core}), // (3 bits) Mode control
+ //.vddio(vdd),
+ //.vddio_q(vdd),
+ //.vdda(vdd),
+ //.vccd(vdd1v8),
+ //.vswitch(vdd),
+ //.vcchib(vdd1v8),
+ //.vssa(vss),
+ //.vssd(vss),
+ //.vssio_q(vss),
+ //.vssio(vss),
+ //.pad(flash_io2),
+ .pad_a_noesd_h(), // Direct pad connection
+ .pad_a_esd_0_h(), // Pad connection through 150 ohms
+ .pad_a_esd_1_h(), // Pad connection through 150 ohms
+ //.amuxbus_a(analog_a),
+ //.amuxbus_b(analog_b),
+ .in(flash_io2_di_core), // Signal from pad to core
+ .in_h(),
+ .tie_hi_esd(),
+ .tie_lo_esd(loopb20)
+ );
+
+ s8iom0_gpiov2_pad flash_io3_pad (
+ .out(flash_io3_do_core), // Signal from core to pad
+ .oe_n(flash_io3_oeb_core), // Output enable (sense inverted)
+ .hld_h_n(vdd), // Hold
+ .enable_h(porb_h), // Enable
+ .enable_inp_h(loopb21), // Enable input buffer
+ .enable_vdda_h(porb_h), //
+ .enable_vswitch_h(vss), //
+ .enable_vddio(vdd1v8), //
+ .inp_dis(flash_io3_ieb_core), // Disable input buffer
+ .ib_mode_sel(vss), //
+ .vtrip_sel(vss), //
+ .slow(vss), //
+ .hld_ovr(vss), //
+ .analog_en(vss), //
+ .analog_sel(vss), //
+ .analog_pol(vss), //
+ .dm({flash_io3_ieb_core, flash_io3_ieb_core, flash_io3_oeb_core}), // (3 bits) Mode control
+ //.vddio(vdd),
+ //.vddio_q(vdd),
+ //.vdda(vdd),
+ //.vccd(vdd1v8),
+ //.vswitch(vdd),
+ //.vcchib(vdd1v8),
+ //.vssa(vss),
+ //.vssd(vss),
+ //.vssio_q(vss),
+ //.vssio(vss),
+ //.pad(flash_io3),
+ .pad_a_noesd_h(), // Direct pad connection
+ .pad_a_esd_0_h(), // Pad connection through 150 ohms
+ .pad_a_esd_1_h(), // Pad connection through 150 ohms
+ //.amuxbus_a(analog_a),
+ //.amuxbus_b(analog_b),
+ .in(flash_io3_di_core), // Signal from pad to core
+ .in_h(),
+ .tie_hi_esd(),
+ .tie_lo_esd(loopb21)
+ );
+
+ // Instantiate GPIO overvoltage (I2C) compliant cell
+ // (Use this for ser_rx and ser_tx; no reason other than testing
+ // the use of the cell.) (Might be worth adding in the I2C IP from
+ // ravenna just to test on a proper I2C channel.)
+
+ s8iom0s8_top_gpio_ovtv2 ser_rx_pad (
+ .out(vss),
+ .oe_n(vdd1v8),
+ .hld_h_n(vdd),
+ .enable_h(porb_h),
+ .enable_inp_h(loopb22),
+ .enable_vdda_h(porb_h),
+ .enable_vddio(vdd1v8),
+ .enable_vswitch_h(vss),
+ .inp_dis(por),
+ .vtrip_sel(vss),
+ .hys_trim(vdd1v8),
+ .slow(vss),
+ .slew_ctl({vss, vss}), // 2 bits
+ .hld_ovr(vss),
+ .analog_en(vss),
+ .analog_sel(vss),
+ .analog_pol(vss),
+ .dm({vss, vss, vdd1v8}), // 3 bits
+ .ib_mode_sel({vss, vss}), // 2 bits
+ .vinref(vdd1v8),
+ //.vddio(vdd),
+ //.vddio_q(vdd),
+ //.vdda(vdd),
+ //.vccd(vdd1v8),
+ //.vswitch(vdd),
+ //.vcchib(vdd1v8),
+ //.vssa(vss),
+ //.vssd(vss),
+ //.vssio_q(vss),
+ //.vssio(vss),
+ //.pad(ser_rx),
+ .pad_a_noesd_h(),
+ .pad_a_esd_0_h(),
+ .pad_a_esd_1_h(),
+ //.amuxbus_a(analog_a),
+ //.amuxbus_b(analog_b),
+ .in(ser_rx_core),
+ .in_h(),
+ .tie_hi_esd(),
+ .tie_lo_esd()
+ );
+
+ s8iom0s8_top_gpio_ovtv2 ser_tx_pad (
+ .out(ser_tx_core),
+ .oe_n(vss),
+ .hld_h_n(vdd),
+ .enable_h(porb_h),
+ .enable_inp_h(loopb23),
+ .enable_vdda_h(porb_h),
+ .enable_vddio(vdd1v8),
+ .enable_vswitch_h(vss),
+ .inp_dis(vdd1v8),
+ .vtrip_sel(vss),
+ .hys_trim(vdd1v8),
+ .slow(vss),
+ .slew_ctl({vss, vss}), // 2 bits
+ .hld_ovr(vss),
+ .analog_en(vss),
+ .analog_sel(vss),
+ .analog_pol(vss),
+ .dm({vdd1v8, vdd1v8, vss}), // 3 bits
+ .ib_mode_sel({vss, vss}), // 2 bits
+ .vinref(vdd1v8),
+ //.vddio(vdd),
+ //.vddio_q(vdd),
+ //.vdda(vdd),
+ //.vccd(vdd1v8),
+ //.vswitch(vdd),
+ //.vcchib(vdd1v8),
+ //.vssa(vss),
+ //.vssd(vss),
+ //.vssio_q(vss),
+ //.vssio(vss),
+ //.pad(ser_tx),
+ .pad_a_noesd_h(),
+ .pad_a_esd_0_h(),
+ .pad_a_esd_1_h(),
+ //.amuxbus_a(analog_a),
+ //.amuxbus_b(analog_b),
+ .in(),
+ .in_h(),
+ .tie_hi_esd(),
+ .tie_lo_esd()
+ );
+/*
+ // Corner cells (These are overlay cells; it is not clear what is normally
+ // supposed to go under them.)
+ s8iom0_corner_pad corner [3:0] (
+ //.vssio(vss),
+ //.vddio(vdd),
+ //.vddio_q(vdd),
+ //.vssio_q(vss),
+ //.amuxbus_a(analog_a),
+ //.amuxbus_b(analog_b),
+ //.vssd(vss),
+ //.vssa(vss),
+ //.vswitch(vdd),
+ //.vdda(vdd),
+ //.vccd(vdd1v8),
+ //.vcchib(vdd1v8)
+ );
+*/
+ // SoC core
+
+ wire [9:0] adc0_data_core;
+ wire [1:0] adc0_inputsrc_core;
+ wire [9:0] adc1_data_core;
+ wire [1:0] adc1_inputsrc_core;
+ wire [9:0] dac_value_core;
+ wire [1:0] comp_ninputsrc_core;
+ wire [1:0] comp_pinputsrc_core;
+ wire [7:0] spi_ro_config_core;
+
+ wire striVe_clk, striVe_rstn;
+
+ striVe_clkrst clkrst(
+`ifdef LVS
+ .vdd1v8(vdd1v8),
+ .vss(vss),
+`endif
+ .ext_clk_sel(ext_clk_sel_core),
+ .ext_clk(ext_clk_core),
+ .pll_clk(pll_clk_core),
+ .reset(por),
+ .ext_reset(ext_reset_core),
+ .clk(striVe_clk),
+ .resetn(striVe_rstn)
+);
+
+ striVe_soc core (
+`ifdef LVS
+ .vdd1v8(vdd1v8),
+ .vss(vss),
+`endif
+
+ .pll_clk(pll_clk_core),
+ .ext_clk(ext_clk_core),
+ .ext_clk_sel(ext_clk_sel_core),
+ /*
+ .ext_reset(ext_reset_core),
+ .reset(por),
+ */
+ .clk(striVe_clk),
+ .resetn(striVe_rstn),
+ .gpio_out_pad(gpio_out_core),
+ .gpio_in_pad(gpio_in_core),
+ .gpio_mode0_pad(gpio_mode0_core),
+ .gpio_mode1_pad(gpio_mode1_core),
+ .gpio_outenb_pad(gpio_outenb_core),
+ .gpio_inenb_pad(gpio_inenb_core),
+ .adc0_ena(adc0_ena_core),
+ .adc0_convert(adc0_convert_core),
+ .adc0_data(adc0_data_core),
+ .adc0_done(adc0_done_core),
+ .adc0_clk(adc0_clk_core),
+ .adc0_inputsrc(adc0_inputsrc_core),
+ .adc1_ena(adc1_ena_core),
+ .adc1_convert(adc1_convert_core),
+ .adc1_clk(adc1_clk_core),
+ .adc1_inputsrc(adc1_inputsrc_core),
+ .adc1_data(adc1_data_core),
+ .adc1_done(adc1_done_core),
+ .dac_ena(dac_ena_core),
+ .dac_value(dac_value_core),
+ .analog_out_sel(analog_out_sel_core),
+ .opamp_ena(opamp_ena_core),
+ .opamp_bias_ena(opamp_bias_ena_core),
+ .bg_ena(bg_ena_core),
+ .comp_ena(comp_ena_core),
+ .comp_ninputsrc(comp_ninputsrc_core),
+ .comp_pinputsrc(comp_pinputsrc_core),
+ .rcosc_ena(rcosc_ena_core),
+ .overtemp_ena(overtemp_ena_core),
+ .overtemp(overtemp_core),
+ .rcosc_in(rcosc_in_core),
+ .xtal_in(xtal_in_core),
+ .comp_in(comp_in_core),
+ .spi_sck(SCK_core),
+ .spi_ro_config(spi_ro_config_core),
+ .spi_ro_xtal_ena(spi_ro_xtal_ena_core),
+ .spi_ro_reg_ena(spi_ro_reg_ena_core),
+ .spi_ro_pll_dco_ena(spi_ro_pll_dco_ena_core),
+ .spi_ro_pll_div(spi_ro_pll_div_core),
+ .spi_ro_pll_sel(spi_ro_pll_sel_core),
+ .spi_ro_pll_trim(spi_ro_pll_trim_core),
+ .spi_ro_mfgr_id(spi_ro_mfgr_id_core),
+ .spi_ro_prod_id(spi_ro_prod_id_core),
+ .spi_ro_mask_rev(spi_ro_mask_rev_core),
+ .ser_tx(ser_tx_core),
+ .ser_rx(ser_rx_core),
+ .irq_pin(irq_pin_core),
+ .irq_spi(irq_spi_core),
+ .trap(trap_core),
+ .flash_csb(flash_csb_core),
+ .flash_clk(flash_clk_core),
+ .flash_csb_oeb(flash_csb_oeb_core),
+ .flash_clk_oeb(flash_clk_oeb_core),
+ .flash_io0_oeb(flash_io0_oeb_core),
+ .flash_io1_oeb(flash_io1_oeb_core),
+ .flash_io2_oeb(flash_io2_oeb_core),
+ .flash_io3_oeb(flash_io3_oeb_core),
+ .flash_csb_ieb(flash_csb_ieb_core),
+ .flash_clk_ieb(flash_clk_ieb_core),
+ .flash_io0_ieb(flash_io0_ieb_core),
+ .flash_io1_ieb(flash_io1_ieb_core),
+ .flash_io2_ieb(flash_io2_ieb_core),
+ .flash_io3_ieb(flash_io3_ieb_core),
+ .flash_io0_do(flash_io0_do_core),
+ .flash_io1_do(flash_io1_do_core),
+ .flash_io2_do(flash_io2_do_core),
+ .flash_io3_do(flash_io3_do_core),
+ .flash_io0_di(flash_io0_di_core),
+ .flash_io1_di(flash_io1_di_core),
+ .flash_io2_di(flash_io2_di_core),
+ .flash_io3_di(flash_io3_di_core)
+ );
+
+ // For the mask revision input, use an array of digital constant logic cells
+
+ wire [3:0] mask_rev;
+
+ scs8hd_conb_1 mask_rev_value [3:0] (
+`ifdef LVS
+ .vpwr(vdd1v8),
+ .vpb(vdd1v8),
+ .vnb(vss),
+ .vgnd(vss),
+`endif
+ .HI(),
+ .LO(mask_rev)
+ );
+
+ // Housekeeping SPI at 1.8V.
+
+ striVe_spi housekeeping (
+`ifdef LVS
+ .vdd(vdd1v8),
+ .vss(vss),
+`endif
+ .RSTB(porb),
+ .SCK(SCK_core),
+ .SDI(SDI_core),
+ .CSB(CSB_core),
+ .SDO(SDO_core),
+ .sdo_enb(SDO_enb),
+ .xtal_ena(spi_ro_xtal_ena_core),
+ .reg_ena(spi_ro_reg_ena_core),
+ .pll_dco_ena(spi_ro_pll_dco_ena_core),
+ .pll_sel(spi_ro_pll_sel_core),
+ .pll_div(spi_ro_pll_div_core),
+ .pll_trim(spi_ro_pll_trim_core),
+ .pll_bypass(ext_clk_sel_core),
+ .irq(irq_spi_core),
+ .RST(por),
+ .reset(ext_reset_core),
+ .trap(trap_core),
+ .mfgr_id(spi_ro_mfgr_id_core),
+ .prod_id(spi_ro_prod_id_core),
+ .mask_rev_in(mask_rev),
+ .mask_rev(spi_ro_mask_rev_core)
+ );
+
+ lvlshiftdown porb_level_shift (
+`ifdef LVS
+ .vpwr(vdd1v8),
+ .vpb(vdd1v8),
+ .vnb(vss),
+ .vgnd(vss),
+`endif
+ .A(porb_h),
+ .X(porb)
+ );
+
+ // On-board experimental digital PLL
+ // Use xi_core, assumed to be a CMOS digital clock signal. xo_core
+ // is used as an output and set from pll_clk16.
+
+ digital_pll pll (
+`ifdef LVS
+ .vdd(vdd1v8),
+ .vss(vss),
+`endif
+ .reset(por),
+ .extclk_sel(ext_clk_sel_core),
+ .osc(xi_core),
+ .clockc(pll_clk_core),
+ .clockp({pll_clk_core0, pll_clk_core90}),
+ .clockd({pll_clk2, pll_clk4, pll_clk8, pll_clk16}),
+ .div(spi_ro_pll_div_core),
+ .sel(spi_ro_pll_sel_core),
+ .dco(spi_ro_pll_dco_ena_core),
+ .ext_trim(spi_ro_pll_trim_core)
+ );
+
+endmodule
diff --git a/verilog/stubs/power_pads_lib.v b/verilog/stubs/power_pads_lib.v
new file mode 100644
index 0000000..f679280
--- /dev/null
+++ b/verilog/stubs/power_pads_lib.v
@@ -0,0 +1,445 @@
+//-----------------------------------------------------------------------
+// Verilog stub entries for standard power pads (s8 power pads + overlays)
+// Also includes stub entries for the corner and fill cells
+// Also includes the custom gpiov2 cell (adds m5 on buses), which is a wrapper
+// for the s8 gpiov2 cell.
+//
+// This file is distributed as open source under the Apache 2.0 license
+// Copyright 2019 efabless, Inc.
+// Written by Tim Edwards
+//-----------------------------------------------------------------------
+
+(* blackbox *)
+module s8iom0_vccd_hvc_pad (amuxbus_a, amuxbus_b, drn_hvc, ogc_hvc,
+ src_bdy_hvc,vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
+ vssio, vssd, vssio_q
+);
+ inout amuxbus_a;
+ inout amuxbus_b;
+
+ inout ogc_hvc;
+ inout drn_hvc;
+ inout src_bdy_hvc;
+ inout vddio;
+ inout vddio_q;
+ inout vdda;
+ inout vccd;
+ inout vswitch;
+ inout vcchib;
+ inout vssa;
+ inout vssd;
+ inout vssio_q;
+ inout vssio;
+
+endmodule
+
+(* blackbox *)
+module s8iom0_vccd_lvc_pad (amuxbus_a, amuxbus_b,
+ drn_lvc1, drn_lvc2, src_bdy_lvc1, src_bdy_lvc2, bdy2_b2b, vssi, ogc_lvc,
+ vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
+ vssio, vssd, vssio_q
+);
+ inout amuxbus_a;
+ inout amuxbus_b;
+
+ inout drn_lvc1;
+ inout drn_lvc2;
+ inout src_bdy_lvc1;
+ inout src_bdy_lvc2;
+ inout bdy2_b2b;
+ inout vssi;
+ inout ogc_lvc;
+ inout vddio;
+ inout vddio_q;
+ inout vdda;
+ inout vccd;
+ inout vswitch;
+ inout vcchib;
+ inout vssa;
+ inout vssd;
+ inout vssio_q;
+ inout vssio;
+
+endmodule
+
+(* blackbox *)
+module s8iom0_vdda_lvc_pad (amuxbus_a, amuxbus_b,
+ drn_lvc1, drn_lvc2, src_bdy_lvc1, src_bdy_lvc2, bdy2_b2b, vssi, ogc_lvc,
+ vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
+ vssio, vssd, vssio_q
+);
+ inout amuxbus_a;
+ inout amuxbus_b;
+
+ inout drn_lvc1;
+ inout drn_lvc2;
+ inout src_bdy_lvc1;
+ inout src_bdy_lvc2;
+ inout bdy2_b2b;
+ inout vssi;
+ inout ogc_lvc;
+ inout vddio;
+ inout vddio_q;
+ inout vdda;
+ inout vccd;
+ inout vswitch;
+ inout vcchib;
+ inout vssa;
+ inout vssd;
+ inout vssio_q;
+ inout vssio;
+
+endmodule
+
+(* blackbox *)
+module s8iom0_vdda_hvc_pad (amuxbus_a, amuxbus_b, drn_hvc, ogc_hvc,
+ src_bdy_hvc,vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
+ vssio, vssd, vssio_q
+);
+ inout amuxbus_a;
+ inout amuxbus_b;
+
+ inout ogc_hvc;
+ inout drn_hvc;
+ inout src_bdy_hvc;
+ inout vddio;
+ inout vddio_q;
+ inout vdda;
+ inout vccd;
+ inout vswitch;
+ inout vcchib;
+ inout vssa;
+ inout vssd;
+ inout vssio_q;
+ inout vssio;
+
+endmodule
+
+(* blackbox *)
+module s8iom0_vddio_lvc_pad (amuxbus_a, amuxbus_b,
+ drn_lvc1, drn_lvc2, src_bdy_lvc1, src_bdy_lvc2, bdy2_b2b, vssi, ogc_lvc,
+ vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
+ vssio, vssd, vssio_q
+);
+ inout amuxbus_a;
+ inout amuxbus_b;
+
+ inout drn_lvc1;
+ inout drn_lvc2;
+ inout src_bdy_lvc1;
+ inout src_bdy_lvc2;
+ inout bdy2_b2b;
+ inout vssi;
+ inout ogc_lvc;
+ inout vddio;
+ inout vddio_q;
+ inout vdda;
+ inout vccd;
+ inout vswitch;
+ inout vcchib;
+ inout vssa;
+ inout vssd;
+ inout vssio_q;
+ inout vssio;
+
+endmodule
+
+(* blackbox *)
+module s8iom0_vddio_hvc_pad (amuxbus_a, amuxbus_b, drn_hvc, ogc_hvc,
+ src_bdy_hvc,vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
+ vssio, vssd, vssio_q
+);
+ inout amuxbus_a;
+ inout amuxbus_b;
+
+ inout ogc_hvc;
+ inout drn_hvc;
+ inout src_bdy_hvc;
+ inout vddio;
+ inout vddio_q;
+ inout vdda;
+ inout vccd;
+ inout vswitch;
+ inout vcchib;
+ inout vssa;
+ inout vssd;
+ inout vssio_q;
+ inout vssio;
+
+endmodule
+
+(* blackbox *)
+module s8iom0_vssd_lvc_pad (amuxbus_a, amuxbus_b,
+ drn_lvc1, drn_lvc2, src_bdy_lvc1, src_bdy_lvc2, bdy2_b2b, vssi, ogc_lvc,
+ vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
+ vssio, vssd, vssio_q
+);
+ inout amuxbus_a;
+ inout amuxbus_b;
+
+ inout drn_lvc1;
+ inout drn_lvc2;
+ inout src_bdy_lvc1;
+ inout src_bdy_lvc2;
+ inout bdy2_b2b;
+ inout vssi;
+ inout ogc_lvc;
+ inout vddio;
+ inout vddio_q;
+ inout vdda;
+ inout vccd;
+ inout vswitch;
+ inout vcchib;
+ inout vssa;
+ inout vssd;
+ inout vssio_q;
+ inout vssio;
+
+endmodule
+
+(* blackbox *)
+module s8iom0_vssd_hvc_pad (amuxbus_a, amuxbus_b, drn_hvc, ogc_hvc,
+ src_bdy_hvc,vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
+ vssio, vssd, vssio_q
+);
+ inout amuxbus_a;
+ inout amuxbus_b;
+
+ inout ogc_hvc;
+ inout drn_hvc;
+ inout src_bdy_hvc;
+ inout vddio;
+ inout vddio_q;
+ inout vdda;
+ inout vccd;
+ inout vswitch;
+ inout vcchib;
+ inout vssa;
+ inout vssd;
+ inout vssio_q;
+ inout vssio;
+
+endmodule
+
+(* blackbox *)
+module s8iom0_vssio_lvc_pad (amuxbus_a, amuxbus_b,
+ drn_lvc1, drn_lvc2, src_bdy_lvc1, src_bdy_lvc2, bdy2_b2b, vssi, ogc_lvc,
+ vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
+ vssio, vssd, vssio_q
+);
+ inout amuxbus_a;
+ inout amuxbus_b;
+
+ inout drn_lvc1;
+ inout drn_lvc2;
+ inout src_bdy_lvc1;
+ inout src_bdy_lvc2;
+ inout bdy2_b2b;
+ inout vssi;
+ inout ogc_lvc;
+ inout vddio;
+ inout vddio_q;
+ inout vdda;
+ inout vccd;
+ inout vswitch;
+ inout vcchib;
+ inout vssa;
+ inout vssd;
+ inout vssio_q;
+ inout vssio;
+
+endmodule
+
+
+(* blackbox *)
+module s8iom0_vssio_hvc_pad (amuxbus_a, amuxbus_b, drn_hvc, ogc_hvc,
+ src_bdy_hvc,vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
+ vssio, vssd, vssio_q
+);
+ inout amuxbus_a;
+ inout amuxbus_b;
+
+ inout ogc_hvc;
+ inout drn_hvc;
+ inout src_bdy_hvc;
+ inout vddio;
+ inout vddio_q;
+ inout vdda;
+ inout vccd;
+ inout vswitch;
+ inout vcchib;
+ inout vssa;
+ inout vssd;
+ inout vssio_q;
+ inout vssio;
+
+endmodule
+
+(* blackbox *)
+module s8iom0_vssa_lvc_pad (amuxbus_a, amuxbus_b,
+ drn_lvc1, drn_lvc2, src_bdy_lvc1, src_bdy_lvc2, bdy2_b2b, vssi, ogc_lvc,
+ vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
+ vssio, vssd, vssio_q
+);
+ inout amuxbus_a;
+ inout amuxbus_b;
+
+ inout drn_lvc1;
+ inout drn_lvc2;
+ inout src_bdy_lvc1;
+ inout src_bdy_lvc2;
+ inout bdy2_b2b;
+ inout vssi;
+ inout ogc_lvc;
+ inout vddio;
+ inout vddio_q;
+ inout vdda;
+ inout vccd;
+ inout vswitch;
+ inout vcchib;
+ inout vssa;
+ inout vssd;
+ inout vssio_q;
+ inout vssio;
+
+endmodule
+
+(* blackbox *)
+module s8iom0_vssa_hvc_pad (amuxbus_a, amuxbus_b, drn_hvc, ogc_hvc,
+ src_bdy_hvc,vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
+ vssio, vssd, vssio_q
+);
+ inout amuxbus_a;
+ inout amuxbus_b;
+
+ inout ogc_hvc;
+ inout drn_hvc;
+ inout src_bdy_hvc;
+ inout vddio;
+ inout vddio_q;
+ inout vdda;
+ inout vccd;
+ inout vswitch;
+ inout vcchib;
+ inout vssa;
+ inout vssd;
+ inout vssio_q;
+ inout vssio;
+
+endmodule
+
+(* blackbox *)
+module s8iom0_corner_pad (amuxbus_a, amuxbus_b,
+ vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
+ vssio, vssd, vssio_q
+);
+ inout amuxbus_a;
+ inout amuxbus_b;
+
+ inout vddio;
+ inout vddio_q;
+ inout vdda;
+ inout vccd;
+ inout vswitch;
+ inout vcchib;
+ inout vssa;
+ inout vssd;
+ inout vssio_q;
+ inout vssio;
+
+endmodule
+
+(* blackbox *)
+module s8iom0s8_com_bus_slice (amuxbus_a, amuxbus_b,
+ vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
+ vssio, vssd, vssio_q
+);
+ inout amuxbus_a;
+ inout amuxbus_b;
+
+ inout vddio;
+ inout vddio_q;
+ inout vdda;
+ inout vccd;
+ inout vswitch;
+ inout vcchib;
+ inout vssa;
+ inout vssd;
+ inout vssio_q;
+ inout vssio;
+
+endmodule
+
+(* blackbox *)
+module s8iom0s8_com_bus_slice_1um (amuxbus_a, amuxbus_b,
+ ogc_hvc, drn_hvc, src_bdy_hvc,
+ vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
+ vssio, vssd, vssio_q
+);
+ inout amuxbus_a;
+ inout amuxbus_b;
+
+ inout ogc_hvc;
+ inout drn_hvc;
+ inout src_bdy_hvc;
+ inout vddio;
+ inout vddio_q;
+ inout vdda;
+ inout vccd;
+ inout vswitch;
+ inout vcchib;
+ inout vssa;
+ inout vssd;
+ inout vssio_q;
+ inout vssio;
+
+endmodule
+
+(* blackbox *)
+module s8iom0_gpiov2_pad (in_h, pad_a_noesd_h, pad_a_esd_0_h, pad_a_esd_1_h,
+ pad, dm, hld_h_n, in, inp_dis, ib_mode_sel, enable_h, enable_vdda_h,
+ enable_inp_h, oe_n, tie_hi_esd, tie_lo_esd, slow, vtrip_sel, hld_ovr,
+ analog_en, analog_sel, enable_vddio, enable_vswitch_h, analog_pol, out,
+ amuxbus_a, amuxbus_b,vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
+ vssio, vssd, vssio_q
+ );
+
+input out;
+input oe_n;
+input hld_h_n;
+input enable_h;
+input enable_inp_h;
+input enable_vdda_h;
+input enable_vswitch_h;
+input enable_vddio;
+input inp_dis;
+input ib_mode_sel;
+input vtrip_sel;
+input slow;
+input hld_ovr;
+input analog_en;
+input analog_sel;
+input analog_pol;
+input [2:0] dm;
+
+ inout vddio;
+ inout vddio_q;
+ inout vdda;
+ inout vccd;
+ inout vswitch;
+ inout vcchib;
+ inout vssa;
+ inout vssd;
+ inout vssio_q;
+ inout vssio;
+
+inout pad;
+inout pad_a_noesd_h,pad_a_esd_0_h,pad_a_esd_1_h;
+inout amuxbus_a;
+inout amuxbus_b;
+
+output in;
+output in_h;
+output tie_hi_esd, tie_lo_esd;
+
+endmodule
diff --git a/verilog/stubs/s8iom0s8.v b/verilog/stubs/s8iom0s8.v
new file mode 100644
index 0000000..3a20c0d
--- /dev/null
+++ b/verilog/stubs/s8iom0s8.v
@@ -0,0 +1,101 @@
+(* blackbox *)
+module s8iom0s8_top_gpio_ovtv2 ( in, in_h, tie_hi_esd, tie_lo_esd, amuxbus_a,
+ amuxbus_b, pad, pad_a_esd_0_h, pad_a_esd_1_h, pad_a_noesd_h,
+`ifdef USE_PG_PIN
+ vccd, vcchib,vdda, vddio, vddio_q, vssa, vssd, vssio, vssio_q, vswitch,
+`endif
+ analog_en, analog_pol, analog_sel, dm, enable_h, enable_inp_h, enable_vdda_h, enable_vddio, enable_vswitch_h, hld_h_n,
+ hld_ovr, ib_mode_sel, inp_dis, oe_n, out, slow, slew_ctl, vtrip_sel, hys_trim, vinref );
+
+
+input out;
+input oe_n;
+input hld_h_n;
+input enable_h;
+input enable_inp_h;
+input enable_vdda_h;
+input enable_vddio;
+input enable_vswitch_h;
+input inp_dis;
+input vtrip_sel;
+input hys_trim;
+input slow;
+input [1:0] slew_ctl;
+input hld_ovr;
+input analog_en;
+input analog_sel;
+input analog_pol;
+input [2:0] dm;
+input [1:0] ib_mode_sel;
+input vinref;
+
+
+`ifdef USE_PG_PIN
+ inout vddio;
+ inout vddio_q;
+ inout vdda;
+ inout vccd;
+ inout vswitch;
+ inout vcchib;
+ inout vssa;
+ inout vssd;
+ inout vssio_q;
+ inout vssio;
+`endif
+
+inout pad;
+inout pad_a_noesd_h,pad_a_esd_0_h,pad_a_esd_1_h;
+inout amuxbus_a;
+inout amuxbus_b;
+
+output in;
+output in_h;
+output tie_hi_esd, tie_lo_esd;
+
+endmodule
+
+
+(* blackbox *)
+module s8iom0s8_top_xres4v2 ( tie_weak_hi_h, xres_h_n, tie_hi_esd, tie_lo_esd,
+ amuxbus_a, amuxbus_b, pad, pad_a_esd_h, enable_h, en_vddio_sig_h, inp_sel_h, filt_in_h,
+ disable_pullup_h, pullup_h, enable_vddio
+`ifdef USE_PG_PIN
+ ,vccd, vcchib, vdda, vddio,vddio_q, vssa, vssd, vssio, vssio_q, vswitch
+`endif
+ );
+
+ output xres_h_n;
+ inout amuxbus_a;
+ inout amuxbus_b;
+ inout pad;
+ input disable_pullup_h;
+ input enable_h;
+ input en_vddio_sig_h;
+ input inp_sel_h;
+ input filt_in_h;
+ inout pullup_h;
+ input enable_vddio;
+
+`ifdef USE_PG_PIN
+
+ input vccd;
+ input vcchib;
+ input vdda;
+ input vddio;
+ input vddio_q;
+ input vssa;
+ input vssd;
+ input vssio;
+ input vssio_q;
+ input vswitch;
+
+
+
+`endif
+
+ inout pad_a_esd_h;
+ output tie_hi_esd;
+ output tie_lo_esd;
+ inout tie_weak_hi_h;
+endmodule
+
diff --git a/verilog/stubs/scs8hd_conb_1.v b/verilog/stubs/scs8hd_conb_1.v
new file mode 100644
index 0000000..b1fa33a
--- /dev/null
+++ b/verilog/stubs/scs8hd_conb_1.v
@@ -0,0 +1,2 @@
+(* blackbox *)
+module scs8hd_conb_1(output HI, output LO); endmodule
