tree 817df59038378486d42606cd429fd09812efcfba
parent 6c580d773431a08541376b95c099bafe9b28c35b
author Tim Edwards <tim@opencircuitdesign.com> 1586548218 -0400
committer Tim Edwards <tim@opencircuitdesign.com> 1586548218 -0400

Additional corrections for top-level DRC and LVS.  Re-extracted,
generated new netlist, ran LVS, and generated new GDS.  Corrected
the verilog to separate vddio_q and vssio_q as they are supposed
to be (thought that was already done. . . why not?).  Corrected
both the verilog and layout to connect the flash_clk and flash_csb
oeb and ieb lines between the core and padframe (these were missed
due to mixing of sources from the first two revisions of the raven
chip).