/* striVe black-box stub definitions */

module digital_pll(reset, extclk_sel, osc, clockc, clockp, clockd, div, sel, dco, ext_trim
  output clockc;
  output [3:0] clockd;
  output [1:0] clockp;
  input dco;
  input [4:0] div;
  input [25:0] ext_trim;
  input extclk_sel;
  input osc;
  input reset;
  input [2:0] sel;
endmodule

module striVe_clkrst(ext_clk_sel, ext_clk, pll_clk, reset, ext_reset, clk, resetn);
  output clk;
  input ext_clk;
  input ext_clk_sel;
  input ext_reset;
  input pll_clk;
  input reset;
  wire [2:0] reset_delay;
  output resetn;
endmodule

module striVe_spi(RSTB, SCK, SDI, CSB, SDO, sdo_enb, xtal_ena, reg_ena, pll_dco_ena, pll_d
iv, pll_sel, pll_trim, pll_bypass, irq, reset, RST, trap, mfgr_id, prod_id, mask_rev_in, m
ask_rev);
  input CSB;
  output RST;
  input RSTB;
  input SCK;
  input SDI;
  output SDO;
  output irq;
  output [3:0] mask_rev;
  input [3:0] mask_rev_in;
  output [11:0] mfgr_id;
  output pll_bypass;
  output pll_dco_ena;
  output [4:0] pll_div;
  output [2:0] pll_sel;
  output [25:0] pll_trim;
  output [7:0] prod_id;
  output reg_ena;
  output reset;
  output sdo_enb;
  input trap;
  output xtal_ena;
endmodule

module striVe_soc (pll_clk,
    ext_clk,
    ext_clk_sel,
    clk,
    resetn,
    adc0_ena,
    adc0_convert,
    adc0_done,
    adc0_clk,
    adc1_ena,
    adc1_convert,
    adc1_clk,
    adc1_done,
    dac_ena,
    analog_out_sel,
    opamp_ena,
    opamp_bias_ena,
    bg_ena,
    comp_ena,
    rcosc_ena,
    overtemp_ena,
    overtemp,
    rcosc_in,
    xtal_in,
    comp_in,
    spi_sck,
    spi_ro_xtal_ena,
    spi_ro_reg_ena,
    spi_ro_pll_dco_ena,
    ser_tx,
    ser_rx,
    irq_pin,
    irq_spi,
    trap,
    flash_csb,
    flash_clk,
    flash_csb_oeb,
    flash_clk_oeb,
    flash_io0_oeb,
    flash_io1_oeb,
    flash_io2_oeb,
    flash_io3_oeb,
    flash_csb_ieb,
    flash_clk_ieb,
    flash_io0_ieb,
    flash_io1_ieb,
    flash_io2_ieb,
    flash_io3_ieb,
    flash_io0_do,
    flash_io1_do,
    flash_io2_do,
    flash_io3_do,
    flash_io0_di,
    flash_io1_di,
    flash_io2_di,
    flash_io3_di,
    adc0_data,
    adc0_inputsrc,
    adc1_data,
    adc1_inputsrc,
    comp_ninputsrc,
    comp_pinputsrc,
    dac_value,
    gpio_in_pad,
    gpio_inenb_pad,
    gpio_mode0_pad,
    gpio_mode1_pad,
    gpio_out_pad,
    gpio_outenb_pad,
    spi_ro_config,
    spi_ro_mask_rev,
    spi_ro_mfgr_id,
    spi_ro_pll_div,
    spi_ro_pll_sel,
    spi_ro_pll_trim,
    spi_ro_prod_id);
 input pll_clk;
 input ext_clk;
 input ext_clk_sel;
 input clk;
 input resetn;
 output adc0_ena;
 output adc0_convert;
 input adc0_done;
 output adc0_clk;
 output adc1_ena;
 output adc1_convert;
 output adc1_clk;
 input adc1_done;
 output dac_ena;
 output analog_out_sel;
 output opamp_ena;
 output opamp_bias_ena;
 output bg_ena;
 output comp_ena;
 output rcosc_ena;
 output overtemp_ena;
 input overtemp;
 input rcosc_in;
 input xtal_in;
 input comp_in;
 input spi_sck;
 input spi_ro_xtal_ena;
 input spi_ro_reg_ena;
 input spi_ro_pll_dco_ena;
 output ser_tx;
 input ser_rx;
 input irq_pin;
 input irq_spi;
 output trap;
 output flash_csb;
 output flash_clk;
 output flash_csb_oeb;
 output flash_clk_oeb;
 output flash_io0_oeb;
 output flash_io1_oeb;
 output flash_io2_oeb;
 output flash_io3_oeb;
 output flash_csb_ieb;
 output flash_clk_ieb;
 output flash_io0_ieb;
 output flash_io1_ieb;
 output flash_io2_ieb;
 output flash_io3_ieb;
 output flash_io0_do;
 output flash_io1_do;
 output flash_io2_do;
 output flash_io3_do;
 input flash_io0_di;
 input flash_io1_di;
 input flash_io2_di;
 input flash_io3_di;
 input [9:0] adc0_data;
 output [1:0] adc0_inputsrc;
 input [9:0] adc1_data;
 output [1:0] adc1_inputsrc;
 output [1:0] comp_ninputsrc;
 output [1:0] comp_pinputsrc;
 output [9:0] dac_value;
 input [15:0] gpio_in_pad;
 output [15:0] gpio_inenb_pad;
 output [15:0] gpio_mode0_pad;
 output [15:0] gpio_mode1_pad;
 output [15:0] gpio_out_pad;
 output [15:0] gpio_outenb_pad;
 input [7:0] spi_ro_config;
 input [3:0] spi_ro_mask_rev;
 input [11:0] spi_ro_mfgr_id;
 input [4:0] spi_ro_pll_div;
 input [2:0] spi_ro_pll_sel;
 input [25:0] spi_ro_pll_trim;
 input [7:0] spi_ro_prod_id;
endmodule

module lvlshiftdown (vpwr, vpb, vnb, vgnd, A, X);
 input vpwr;
 input vpb;
 input vnb;
 input vgnd;
 input A;
 output X;
endmodule


//-----------------------------------------------------------------------
// Verilog stub entries for standard power pads (s8 power pads + overlays)
// Also includes stub entries for the corner and fill cells
// Also includes the custom gpiov2 cell (adds m5 on buses), which is a wrapper
// for the s8 gpiov2 cell.
//
// This file is distributed as open source under the Apache 2.0 license
// Copyright 2019 efabless, Inc.
// Written by Tim Edwards 
//-----------------------------------------------------------------------

module s8iom0_vccd_hvc_pad (amuxbus_a, amuxbus_b, drn_hvc, ogc_hvc,
	src_bdy_hvc,vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
	vssio, vssd, vssio_q
);
  inout amuxbus_a;
  inout amuxbus_b;

  inout ogc_hvc;
  inout drn_hvc;
  inout src_bdy_hvc;
  inout vddio;	
  inout vddio_q;	
  inout vdda;
  inout vccd;
  inout vswitch;
  inout vcchib;
  inout vssa;
  inout vssd;
  inout vssio_q;
  inout vssio;

endmodule

module s8iom0_vccd_lvc_pad (amuxbus_a, amuxbus_b,
	drn_lvc1, drn_lvc2, src_bdy_lvc1, src_bdy_lvc2, bdy2_b2b, ogc_lvc,
	vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
	vssio, vssd, vssio_q
);
  inout amuxbus_a;
  inout amuxbus_b;

  inout drn_lvc1;
  inout drn_lvc2;
  inout src_bdy_lvc1;
  inout src_bdy_lvc2;
  inout bdy2_b2b;
  inout	ogc_lvc;
  inout vddio;	
  inout vddio_q;	
  inout vdda;
  inout vccd;
  inout vswitch;
  inout vcchib;
  inout vssa;
  inout vssd;
  inout vssio_q;
  inout vssio;

endmodule

module s8iom0_vdda_lvc_pad (amuxbus_a, amuxbus_b,
	drn_lvc1, drn_lvc2, src_bdy_lvc1, src_bdy_lvc2, bdy2_b2b, ogc_lvc,
	vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
	vssio, vssd, vssio_q
);
  inout amuxbus_a;
  inout amuxbus_b;

  inout drn_lvc1;
  inout drn_lvc2;
  inout src_bdy_lvc1;
  inout src_bdy_lvc2;
  inout bdy2_b2b;
  inout	ogc_lvc;
  inout vddio;	
  inout vddio_q;	
  inout vdda;
  inout vccd;
  inout vswitch;
  inout vcchib;
  inout vssa;
  inout vssd;
  inout vssio_q;
  inout vssio;

endmodule

module s8iom0_vdda_hvc_pad (amuxbus_a, amuxbus_b, drn_hvc, ogc_hvc,
	src_bdy_hvc,vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
	vssio, vssd, vssio_q
);
  inout amuxbus_a;
  inout amuxbus_b;

  inout ogc_hvc;
  inout drn_hvc;
  inout src_bdy_hvc;
  inout vddio;	
  inout vddio_q;	
  inout vdda;
  inout vccd;
  inout vswitch;
  inout vcchib;
  inout vssa;
  inout vssd;
  inout vssio_q;
  inout vssio;

endmodule

module s8iom0_vddio_lvc_pad (amuxbus_a, amuxbus_b,
	drn_lvc1, drn_lvc2, src_bdy_lvc1, src_bdy_lvc2, bdy2_b2b, ogc_lvc,
	vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
	vssio, vssd, vssio_q
);
  inout amuxbus_a;
  inout amuxbus_b;

  inout drn_lvc1;
  inout drn_lvc2;
  inout src_bdy_lvc1;
  inout src_bdy_lvc2;
  inout bdy2_b2b;
  inout	ogc_lvc;
  inout vddio;	
  inout vddio_q;	
  inout vdda;
  inout vccd;
  inout vswitch;
  inout vcchib;
  inout vssa;
  inout vssd;
  inout vssio_q;
  inout vssio;

endmodule

module s8iom0_vddio_hvc_pad (amuxbus_a, amuxbus_b, drn_hvc, ogc_hvc,
	src_bdy_hvc,vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
	vssio, vssd, vssio_q
);
  inout amuxbus_a;
  inout amuxbus_b;

  inout ogc_hvc;
  inout drn_hvc;
  inout src_bdy_hvc;
  inout vddio;	
  inout vddio_q;	
  inout vdda;
  inout vccd;
  inout vswitch;
  inout vcchib;
  inout vssa;
  inout vssd;
  inout vssio_q;
  inout vssio;

endmodule

module s8iom0_vssd_lvc_pad (amuxbus_a, amuxbus_b,
	drn_lvc1, drn_lvc2, src_bdy_lvc1, src_bdy_lvc2, bdy2_b2b, ogc_lvc,
	vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
	vssio, vssd, vssio_q
);
  inout amuxbus_a;
  inout amuxbus_b;

  inout drn_lvc1;
  inout drn_lvc2;
  inout src_bdy_lvc1;
  inout src_bdy_lvc2;
  inout bdy2_b2b;
  inout	ogc_lvc;
  inout vddio;	
  inout vddio_q;	
  inout vdda;
  inout vccd;
  inout vswitch;
  inout vcchib;
  inout vssa;
  inout vssd;
  inout vssio_q;
  inout vssio;

endmodule

module s8iom0_vssd_hvc_pad (amuxbus_a, amuxbus_b, drn_hvc, ogc_hvc,
	src_bdy_hvc,vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
	vssio, vssd, vssio_q
);
  inout amuxbus_a;
  inout amuxbus_b;

  inout ogc_hvc;
  inout drn_hvc;
  inout src_bdy_hvc;
  inout vddio;	
  inout vddio_q;	
  inout vdda;
  inout vccd;
  inout vswitch;
  inout vcchib;
  inout vssa;
  inout vssd;
  inout vssio_q;
  inout vssio;

endmodule

module s8iom0_vssio_lvc_pad (amuxbus_a, amuxbus_b,
	drn_lvc1, drn_lvc2, src_bdy_lvc1, src_bdy_lvc2, bdy2_b2b, ogc_lvc,
	vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
	vssio, vssd, vssio_q
);
  inout amuxbus_a;
  inout amuxbus_b;

  inout drn_lvc1;
  inout drn_lvc2;
  inout src_bdy_lvc1;
  inout src_bdy_lvc2;
  inout bdy2_b2b;
  inout	ogc_lvc;
  inout vddio;	
  inout vddio_q;	
  inout vdda;
  inout vccd;
  inout vswitch;
  inout vcchib;
  inout vssa;
  inout vssd;
  inout vssio_q;
  inout vssio;

endmodule


module s8iom0_vssio_hvc_pad (amuxbus_a, amuxbus_b, drn_hvc, ogc_hvc,
	src_bdy_hvc,vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
	vssio, vssd, vssio_q
);
  inout amuxbus_a;
  inout amuxbus_b;

  inout ogc_hvc;
  inout drn_hvc;
  inout src_bdy_hvc;
  inout vddio;	
  inout vddio_q;	
  inout vdda;
  inout vccd;
  inout vswitch;
  inout vcchib;
  inout vssa;
  inout vssd;
  inout vssio_q;
  inout vssio;

endmodule

module s8iom0_vssa_lvc_pad (amuxbus_a, amuxbus_b,
	drn_lvc1, drn_lvc2, src_bdy_lvc1, src_bdy_lvc2, bdy2_b2b, ogc_lvc,
	vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
	vssio, vssd, vssio_q
);
  inout amuxbus_a;
  inout amuxbus_b;

  inout drn_lvc1;
  inout drn_lvc2;
  inout src_bdy_lvc1;
  inout src_bdy_lvc2;
  inout bdy2_b2b;
  inout	ogc_lvc;
  inout vddio;	
  inout vddio_q;	
  inout vdda;
  inout vccd;
  inout vswitch;
  inout vcchib;
  inout vssa;
  inout vssd;
  inout vssio_q;
  inout vssio;

endmodule

module s8iom0_vssa_hvc_pad (amuxbus_a, amuxbus_b, drn_hvc, ogc_hvc,
	src_bdy_hvc,vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
	vssio, vssd, vssio_q
);
  inout amuxbus_a;
  inout amuxbus_b;

  inout ogc_hvc;
  inout drn_hvc;
  inout src_bdy_hvc;
  inout vddio;	
  inout vddio_q;	
  inout vdda;
  inout vccd;
  inout vswitch;
  inout vcchib;
  inout vssa;
  inout vssd;
  inout vssio_q;
  inout vssio;

endmodule

module s8iom0_corner_pad (amuxbus_a, amuxbus_b, 
	vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
	vssio, vssd, vssio_q
);
  inout amuxbus_a;
  inout amuxbus_b;

  inout vddio;	
  inout vddio_q;	
  inout vdda;
  inout vccd;
  inout vswitch;
  inout vcchib;
  inout vssa;
  inout vssd;
  inout vssio_q;
  inout vssio;

endmodule

module s8iom0s8_com_bus_slice (amuxbus_a, amuxbus_b,
	vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
	vssio, vssd, vssio_q
);
  inout amuxbus_a;
  inout amuxbus_b;

  inout vddio;	
  inout vddio_q;	
  inout vdda;
  inout vccd;
  inout vswitch;
  inout vcchib;
  inout vssa;
  inout vssd;
  inout vssio_q;
  inout vssio;

endmodule

module s8iom0s8_com_bus_slice_1um (amuxbus_a, amuxbus_b,
	ogc_hvc, drn_hvc, src_bdy_hvc,
	vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
	vssio, vssd, vssio_q
);
  inout amuxbus_a;
  inout amuxbus_b;

  inout ogc_hvc;
  inout drn_hvc;
  inout src_bdy_hvc;
  inout vddio;	
  inout vddio_q;	
  inout vdda;
  inout vccd;
  inout vswitch;
  inout vcchib;
  inout vssa;
  inout vssd;
  inout vssio_q;
  inout vssio;

endmodule

module s8iom0_gpiov2_pad (in_h, pad_a_noesd_h, pad_a_esd_0_h, pad_a_esd_1_h,
    pad, dm, hld_h_n, in, inp_dis, ib_mode_sel, enable_h, enable_vdda_h,
    enable_inp_h, oe_n, tie_hi_esd, tie_lo_esd, slow, vtrip_sel, hld_ovr,
    analog_en, analog_sel, enable_vddio, enable_vswitch_h, analog_pol, out,
    amuxbus_a, amuxbus_b,vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd,
    vssio, vssd, vssio_q 
    );

input out;  		
input oe_n;  		
input hld_h_n;		
input enable_h;
input enable_inp_h;	
input enable_vdda_h;	
input enable_vswitch_h;	
input enable_vddio;	
input inp_dis;		
input ib_mode_sel;
input vtrip_sel;	
input slow;		
input hld_ovr;		
input analog_en;	
input analog_sel;	
input analog_pol;	
input [2:0] dm;		

	inout vddio;	
	inout vddio_q;	
	inout vdda;
	inout vccd;
	inout vswitch;
	inout vcchib;
	inout vssa;
	inout vssd;
	inout vssio_q;
	inout vssio;

inout pad;
inout pad_a_noesd_h,pad_a_esd_0_h,pad_a_esd_1_h;
inout amuxbus_a;
inout amuxbus_b;

output in;
output in_h;
output tie_hi_esd, tie_lo_esd;

endmodule


module s8iom0s8_top_gpio_ovtv2 ( in, in_h, tie_hi_esd, tie_lo_esd, amuxbus_a,
    amuxbus_b, pad, pad_a_esd_0_h, pad_a_esd_1_h, pad_a_noesd_h, 
    vccd, vcchib,vdda, vddio, vddio_q, vssa, vssd, vssio, vssio_q, vswitch, 
    analog_en, analog_pol, analog_sel, dm, enable_h, enable_inp_h, enable_vdda_h, enable_vddio, enable_vswitch_h, hld_h_n,
    hld_ovr, ib_mode_sel, inp_dis, oe_n, out, slow, slew_ctl, vtrip_sel, hys_trim, vinref );

   
input out;  		
input oe_n;  		
input hld_h_n;		
input enable_h;
input enable_inp_h;	
input enable_vdda_h;	
input enable_vddio;	
input enable_vswitch_h;	
input inp_dis;		
input vtrip_sel;	
input hys_trim;
input slow;
input [1:0] slew_ctl;		
input hld_ovr;		
input analog_en;	
input analog_sel;	
input analog_pol;	
input [2:0] dm;		
input [1:0] ib_mode_sel;
input vinref;


	inout vddio;	
	inout vddio_q;	
	inout vdda;
	inout vccd;
	inout vswitch;
	inout vcchib;
	inout vssa;
	inout vssd;
	inout vssio_q;
	inout vssio;

inout pad;
inout pad_a_noesd_h,pad_a_esd_0_h,pad_a_esd_1_h;
inout amuxbus_a;
inout amuxbus_b;

output in;
output in_h;
output tie_hi_esd, tie_lo_esd;

endmodule


module s8iom0s8_top_xres4v2 ( tie_weak_hi_h,  xres_h_n, tie_hi_esd, tie_lo_esd,
    amuxbus_a, amuxbus_b, pad, pad_a_esd_h, enable_h, en_vddio_sig_h, inp_sel_h, filt_in_h,
    disable_pullup_h, pullup_h, enable_vddio
    ,vccd, vcchib, vdda, vddio,vddio_q, vssa, vssd, vssio, vssio_q, vswitch
     );

    output xres_h_n;
    inout amuxbus_a;
    inout amuxbus_b;
    inout pad;
    input disable_pullup_h;
    input enable_h; 
    input en_vddio_sig_h; 
    input inp_sel_h; 
    input filt_in_h;
    inout pullup_h;
    input enable_vddio;
    
    input vccd;
    input vcchib;
    input vdda;
    input vddio;
    input vddio_q;
    input vssa;
    input vssd;
    input vssio;
    input vssio_q;
    input vswitch;
    
    
    inout pad_a_esd_h;
    output tie_hi_esd;
    output tie_lo_esd;
    inout tie_weak_hi_h;
endmodule


module scs8hd_conb_1(output HI, output LO);
endmodule