* CACE gensim simulation file ${FILENAME}_${N}
* Generated by CACE gensim, efabless inc. (c) 2017

.lib "/ef/tech/SW/EFS8A/libs.tech/ngspice/s8.lib" ${CORNER}

.option TEMP = ${TEMPERATURE}

.include "${DUT_PATH}"

XDUT ${PIN:A:A} ${PIN:X:X}
+${PIN:VDD3V3:VDD3V3} ${PIN:VDD1V8:VDD1V8} ${PIN:VSS:VSS} ${DUT_NAME}

VVDD33 VDD3V3 VSS DC ${VOLTAGE:VDD3V3}
VVDD18 VDD1V8 VSS DC ${VOLTAGE:VDD1V8}
VVSS VSS 0 DC ${VOLTAGE:VSS}
VVA A VSS DC ${VOLTAGE:A}

.control
op
let iidle18 = -I(VVDD18)
let iidle33 = -I(VVDD33)
let iidle = $&iidle18 + $&iidle33
echo ${FILENAME} $&iidle
quit
.endc
.end