Netgen 1.5.141 compiled on Thu Mar  5 15:50:50 EST 2020
Warning: netgen command 'format' use fully-qualified name '::netgen::format'
Warning: netgen command 'global' use fully-qualified name '::netgen::global'
Generating JSON file result
Reading netlist file ../spi/lvs/striVe_clkrst.spice
Reading netlist file ../verilog/gl/striVe_clkrst.synthesis.v
Warning:  A case-insensitive file has been read and so the	verilog file must be treated case-insensitive to match.
Creating placeholder cell definition for module scs8hd_inv_4.
Creating placeholder cell definition for module scs8hd_nor2_4.
Creating placeholder cell definition for module scs8hd_and2_4.
Creating placeholder cell definition for module scs8hd_a21o_4.
Creating placeholder cell definition for module scs8hd_dfstp_4.
Reading setup file /home/tim/projects/efabless/tech/SW/EFS8A/libs.tech/netgen/EFS8A_setup.tcl
Comparison output logged to file striVe_clkrst_comp.out
Logging to file "striVe_clkrst_comp.out" enabled
Contents of circuit 1:  Circuit: 'scs8hd_dfstp_4'
Circuit scs8hd_dfstp_4 contains 0 device instances.
Circuit contains 0 nets, and 6 disconnected pins.
Contents of circuit 2:  Circuit: 'scs8hd_dfstp_4'
Circuit scs8hd_dfstp_4 contains 0 device instances.
Circuit contains 0 nets.

Circuit scs8hd_dfstp_4 contains no devices.
Contents of circuit 1:  Circuit: 'scs8hd_inv_4'
Circuit scs8hd_inv_4 contains 0 device instances.
Circuit contains 0 nets, and 4 disconnected pins.
Contents of circuit 2:  Circuit: 'scs8hd_inv_4'
Circuit scs8hd_inv_4 contains 0 device instances.
Circuit contains 0 nets.

Circuit scs8hd_inv_4 contains no devices.
Contents of circuit 1:  Circuit: 'scs8hd_a21o_4'
Circuit scs8hd_a21o_4 contains 0 device instances.
Circuit contains 0 nets, and 6 disconnected pins.
Contents of circuit 2:  Circuit: 'scs8hd_a21o_4'
Circuit scs8hd_a21o_4 contains 0 device instances.
Circuit contains 0 nets.

Circuit scs8hd_a21o_4 contains no devices.
Contents of circuit 1:  Circuit: 'scs8hd_and2_4'
Circuit scs8hd_and2_4 contains 0 device instances.
Circuit contains 0 nets, and 5 disconnected pins.
Contents of circuit 2:  Circuit: 'scs8hd_and2_4'
Circuit scs8hd_and2_4 contains 0 device instances.
Circuit contains 0 nets.

Circuit scs8hd_and2_4 contains no devices.
Contents of circuit 1:  Circuit: 'scs8hd_nor2_4'
Circuit scs8hd_nor2_4 contains 0 device instances.
Circuit contains 0 nets, and 5 disconnected pins.
Contents of circuit 2:  Circuit: 'scs8hd_nor2_4'
Circuit scs8hd_nor2_4 contains 0 device instances.
Circuit contains 0 nets.

Circuit scs8hd_nor2_4 contains no devices.
Contents of circuit 1:  Circuit: 'striVe_clkrst'
Circuit striVe_clkrst contains 10 device instances.
  Class: scs8hd_nor2_4         instances:   1
  Class: scs8hd_a21o_4         instances:   1
  Class: scs8hd_inv_4          instances:   4
  Class: scs8hd_dfstp_4        instances:   3
  Class: scs8hd_and2_4         instances:   1
Circuit contains 18 nets.
Contents of circuit 2:  Circuit: 'striVe_clkrst'
Circuit striVe_clkrst contains 10 device instances.
  Class: scs8hd_nor2_4         instances:   1
  Class: scs8hd_a21o_4         instances:   1
  Class: scs8hd_inv_4          instances:   4
  Class: scs8hd_dfstp_4        instances:   3
  Class: scs8hd_and2_4         instances:   1
Circuit contains 16 nets.

Circuit 1 contains 10 devices, Circuit 2 contains 10 devices.
Circuit 1 contains 16 nets,    Circuit 2 contains 16 nets.

Netlists match uniquely.
Result: Circuits match uniquely.
Logging to file "striVe_clkrst_comp.out" disabled
LVS Done.