Google Git
Code Review Generate Password Revoke Passwords Sign in
foss-eda-tools / efabless / designs
NameDescription
striveRISC-V SoC created using sky130_fd_sc_hd and "Logic RAM", containing PicoRv32 + DPLL + management SPI + 1 kbytes memory.strive2RISC-V SoC created using sky130_fd_sc_hd and OpenRAM dual port SRAM block, containing PicoRv32 + DPLL + management SPI + 1 kbytes memory.strive3RISC-V SoC created using OSU standard cells and "Logic RAM", containing PicoRv32 + DPLL + management SPI + 1 kbytes memory.strive4RISC-V SoC created using OSU standard cells and OpenRAM dual port SRAM block, containing PicoRv32 + DPLL + management SPI + 1 kbytes memory.strive5RISC-V SoC created using sky130_fd_sc_hd with array of OpenRAM blocks giving 8 kbytes memory, containing PicoRv32 + DPLL + management SPI + 8 kbytes memory.strive6RISC-V SoC created using sky130_fd_sc_hd, OpenRAM dual port SRAM block and DFT support, containing PicoRv32 + DPLL + management SPI + 1 kbytes memory.strive7Reserved for future RISC-V SoC.strive8Reserved for future RISC-V SoC.strive9Reserved for future RISC-V SoC.