efabless/ - Git at Google

designs/striveRISC-V SoC created using sky130_fd_sc_hd and "Logic RAM", containing PicoRv32 + DPLL + management SPI + 1 kbytes memory.designs/strive2RISC-V SoC created using sky130_fd_sc_hd and OpenRAM dual port SRAM block, containing PicoRv32 + DPLL + management SPI + 1 kbytes memory.designs/strive3RISC-V SoC created using OSU standard cells and "Logic RAM", containing PicoRv32 + DPLL + management SPI + 1 kbytes memory.designs/strive4RISC-V SoC created using OSU standard cells and OpenRAM dual port SRAM block, containing PicoRv32 + DPLL + management SPI + 1 kbytes memory.designs/strive5RISC-V SoC created using sky130_fd_sc_hd with array of OpenRAM blocks giving 8 kbytes memory, containing PicoRv32 + DPLL + management SPI + 8 kbytes memory.designs/strive6RISC-V SoC created using sky130_fd_sc_hd, OpenRAM dual port SRAM block and DFT support, containing PicoRv32 + DPLL + management SPI + 1 kbytes memory.designs/strive7Reserved for future RISC-V SoC.designs/strive8Reserved for future RISC-V SoC.designs/strive9Reserved for future RISC-V SoC.openlaneAutomated RTL to GDS-II flow (OpenROAD tools with SkyWater 130nm PDK).