| commit | 7346361526f7f4611b6096c826cbee071093756a | [log] [tgz] |
|---|---|---|
| author | Janavind <jaravind@aggies.ncat.edu> | Tue Mar 15 18:30:47 2022 -0400 |
| committer | Janavind <jaravind@aggies.ncat.edu> | Tue Mar 15 18:30:47 2022 -0400 |
| tree | 2dc435badc08f904f3c1cd2082a232b56837e120 | |
| parent | 2b58eba0c080fa458e09da2cceff222e9dea0e9e [diff] |
modified: def/user_proj_example.def modified: def/user_project_wrapper.def modified: gds/user_proj_example.gds modified: gds/user_project_wrapper.gds modified: lef/user_proj_example.lef modified: lef/user_project_wrapper.lef modified: mag/user_proj_example.mag modified: mag/user_project_wrapper.mag modified: maglef/user_proj_example.mag modified: maglef/user_project_wrapper.mag modified: openlane/user_proj_example/config.tcl modified: openlane/user_project_wrapper/config.tcl modified: sdc/user_proj_example.sdc modified: sdf/user_proj_example.sdf modified: signoff/user_proj_example/final_summary_report.csv modified: signoff/user_project_wrapper/final_summary_report.csv modified: spef/user_proj_example.spef modified: spi/lvs/user_proj_example.spice modified: spi/lvs/user_project_wrapper.spice modified: verilog/gl/user_proj_example.v modified: verilog/gl/user_project_wrapper.v modified: verilog/rtl/user_proj_example.v modified: verilog/rtl/user_project_wrapper.v sdc/user_project_wrapper.sdc sdf/user_project_wrapper.sdf spef/user_project_wrapper.spef
It's a digital alu_xor having two copies of ALUs, namely: alu1 and alu2. The outputs generated by both the ALUs are XORed to yield any discrepancies between the designs. Any difference in the result turns out to be latch-ups or conditions relating to faults.
References
Refer to README for a quick start of how to use caravel_user_project
Refer to README for this sample project documentation.