f7c7a712b21631456ee81f9146d5a2545c9080c2 - third_party/shuttle/sky130/mpw-004/slot-004

commit	f7c7a712b21631456ee81f9146d5a2545c9080c2	[log] [tgz]
author	Anish <anish@anishsinghani.com>	Sat Dec 25 01:20:28 2021 -0800
committer	Anish <anish@anishsinghani.com>	Sat Dec 25 01:20:28 2021 -0800
tree	3f30966b82ab66eed5ab6be7a7e6dd526b84e7ee

Caravel from mpw-3

.gitignore[Added - diff]
.gitmodules[Added - diff]
LICENSE[Added - diff]
Makefile[Added - diff]
caravel[Added - diff]
def/user_proj_example.def[Added - diff]
def/user_project_wrapper.def[Added - diff]
docs/Makefile[Added - diff]
docs/environment.yml[Added - diff]
docs/requirements.txt[Added - diff]
docs/source/_static/counter_32.png[Added - diff]
docs/source/_static/wrapper.png[Added - diff]
docs/source/conf.py[Added - diff]
docs/source/index.rst[Added - diff]
gds/user_proj_example.gds[Added - diff]
gds/user_project_wrapper.gds[Added - diff]
info.yaml[Added - diff]
lef/user_proj_example.lef[Added - diff]
lef/user_project_wrapper.lef[Added - diff]
mag/user_proj_example.mag[Added - diff]
mag/user_project_wrapper.mag[Added - diff]
maglef/user_proj_example.mag[Added - diff]
maglef/user_project_wrapper.mag[Added - diff]
openlane/.gitignore[Added - diff]
openlane/Makefile[Added - diff]
openlane/user_proj_example/config.tcl[Added - diff]
openlane/user_proj_example/pin_order.cfg[Added - diff]
openlane/user_project_wrapper/config.tcl[Added - diff]
openlane/user_project_wrapper/macro.cfg[Added - diff]
openlane/user_project_wrapper/pin_order.cfg[Added - diff]
signoff/user_proj_example/OPENLANE_VERSION[Added - diff]
signoff/user_proj_example/PDK_SOURCES[Added - diff]
signoff/user_proj_example/final_summary_report.csv[Added - diff]
signoff/user_project_wrapper/OPENLANE_VERSION[Added - diff]
signoff/user_project_wrapper/PDK_SOURCES[Added - diff]
signoff/user_project_wrapper/final_summary_report.csv[Added - diff]
spi/lvs/user_proj_example.spice[Added - diff]
spi/lvs/user_project_wrapper.spice[Added - diff]
verilog/dv/Makefile[Added - diff]
verilog/dv/README.md[Added - diff]
verilog/dv/io_ports/Makefile[Added - diff]
verilog/dv/io_ports/io_ports.c[Added - diff]
verilog/dv/io_ports/io_ports_tb.v[Added - diff]
verilog/dv/la_test1/Makefile[Added - diff]
verilog/dv/la_test1/la_test1.c[Added - diff]
verilog/dv/la_test1/la_test1_tb.v[Added - diff]
verilog/dv/la_test2/Makefile[Added - diff]
verilog/dv/la_test2/la_test2.c[Added - diff]
verilog/dv/la_test2/la_test2_tb.v[Added - diff]
verilog/dv/mprj_stimulus/Makefile[Added - diff]
verilog/dv/mprj_stimulus/mprj_stimulus.c[Added - diff]
verilog/dv/mprj_stimulus/mprj_stimulus_tb.v[Added - diff]
verilog/dv/wb_port/Makefile[Added - diff]
verilog/dv/wb_port/wb_port.c[Added - diff]
verilog/dv/wb_port/wb_port_tb.v[Added - diff]
verilog/gl/user_proj_example.v[Added - diff]
verilog/gl/user_project_wrapper.v[Added - diff]
verilog/rtl/uprj_netlists.v[Added - diff]
verilog/rtl/user_proj_example.v[Added - diff]
verilog/rtl/user_project_wrapper.v[Added - diff]

60 files changed

tree: 3f30966b82ab66eed5ab6be7a7e6dd526b84e7ee