64e451b7d2374d372fd999096adea3f064b01a7d - third_party/shuttle/gf180mcu/mpw-000/slot-022

commit	64e451b7d2374d372fd999096adea3f064b01a7d	[log] [tgz]
author	Baungarten-CINVESTAV <101527680+Baungarten-CINVESTAV@users.noreply.github.com>	Mon Dec 05 12:07:40 2022 -0600
committer	GitHub <noreply@github.com>	Mon Dec 05 12:07:40 2022 -0600
tree	93c71be34a246acf3e53ac65756137a835afff0d

Add files via upload

LICENSE[Added - diff]
Makefile[Added - diff]
README.md[Added - diff]
def/Top_Module_4_ALU.def[Added - diff]
def/user_proj_example.def[Added - diff]
def/user_project_wrapper.def[Added - diff]
docs/Makefile[Added - diff]
docs/environment.yml[Added - diff]
docs/requirements.txt[Added - diff]
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docs/source/conf.py[Added - diff]
docs/source/index.rst[Added - diff]
gds/Top_Module_4_ALU.gds[Added - diff]
gds/user_proj_example.gds[Added - diff]
gds/user_project_wrapper.gds[Added - diff]
lef/Top_Module_4_ALU.lef[Added - diff]
lef/user_proj_example.lef[Added - diff]
lef/user_project_wrapper.lef[Added - diff]
lib/Top_Module_4_ALU.lib[Added - diff]
lib/user_proj_example.lib[Added - diff]
lib/user_project_wrapper.lib[Added - diff]
mag/Top_Module_4_ALU.mag[Added - diff]
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maglef/Top_Module_4_ALU.mag[Added - diff]
maglef/user_proj_example.mag[Added - diff]
maglef/user_project_wrapper.mag[Added - diff]
openlane/Makefile[Added - diff]
openlane/alu/config.tcl[Added - diff]
openlane/alu/config.tcl~[Added - diff]
openlane/user_proj_example/config.tcl[Added - diff]
openlane/user_proj_example/pin_order.cfg[Added - diff]
openlane/user_project_wrapper/config.tcl[Added - diff]
openlane/user_project_wrapper/fixed_dont_change/default_wrapper_cfgs.tcl[Added - diff]
openlane/user_project_wrapper/fixed_dont_change/fixed_wrapper_cfgs.tcl[Added - diff]
openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper.def[Added - diff]
openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper_gf180mcu.def[Added - diff]
openlane/user_project_wrapper/macro.cfg[Added - diff]
openlane/user_project_wrapper/pin_order.cfg[Added - diff]
sdc/Top_Module_4_ALU.sdc[Added - diff]
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sdf/Top_Module_4_ALU.sdf[Added - diff]
sdf/multicorner/nom/user_project_wrapper.ff.sdf[Added - diff]
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sdf/multicorner/nom/user_project_wrapper.tt.sdf[Added - diff]
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sdf/user_project_wrapper.sdf[Added - diff]
signoff/alu/OPENLANE_VERSION[Added - diff]
signoff/alu/PDK_SOURCES[Added - diff]
signoff/alu/metrics.csv[Added - diff]
signoff/user_proj_example/OPENLANE_VERSION[Added - diff]
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signoff/user_project_wrapper/OPENLANE_VERSION[Added - diff]
signoff/user_project_wrapper/PDK_SOURCES[Added - diff]
signoff/user_project_wrapper/metrics.csv[Added - diff]
spef/Top_Module_4_ALU.spef[Added - diff]
spef/multicorner/user_project_wrapper.nom.spef[Added - diff]
spef/user_proj_example.spef[Added - diff]
spef/user_project_wrapper.spef[Added - diff]
spi/lvs/Top_Module_4_ALU.spice[Added - diff]
spi/lvs/user_proj_example.spice[Added - diff]
spi/lvs/user_project_wrapper.spice[Added - diff]
verilog/dv/README.md[Added - diff]
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verilog/gl/Top_Module_4_ALU.v[Added - diff]
verilog/gl/user_proj_example.v[Added - diff]
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verilog/includes/includes.gl+sdf.caravel_user_project[Added - diff]
verilog/includes/includes.gl.caravel_user_project[Added - diff]
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verilog/rtl/user_project_wrapper.v[Added - diff]

86 files changed

tree: 93c71be34a246acf3e53ac65756137a835afff0d

README.md

Testing an ALU using gf180 technology, to support a recently submitted journal article titled, Fast Tape-Out Process of an Embedded System-on-Chip with Vector Instruction Accelerator